A4956 Datasheet, PDF (9/11 Pages) Allegro MicroSystems – Full-Bridge PWM Gate Driver

A4956
Full-Bridge PWM Gate Driver
PACKAGE OUTLINE DRAWINGS
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-220WGGD)
Dimensions in millimeters
NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
4.00 ±0.15
20
1
2
A
4.00 ±0.15
0.30
20
0.95
1
2
0.50
2.45 4.10
21X ^D
0.08 C
+0.05
0.25 _–0.07
+0.15
0.40 _–0.10
0.50 BSC
C
0.75 ±0.05 _SEATING
PLANE
2.45
4.10
C _{PCB Layout Reference View}
B
2
1
20
2.45
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier
2.45
discretion)
C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to
meet application process requirements and PCB layout tolerances; when mounting
on a multilayer PCB, thermal vias at the exposed thermal pad land can improve
thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
ES Package, 20-Pin QFN with Exposed Thermal Pad
Allegro MicroSystems, LLC
9
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com