A1356 Datasheet, PDF (8/20 Pages) Allegro MicroSystems – High Precision Linear Hall-Effect Sensor

A1356
High Precision Linear Hall-Effect Sensor
With an Open Drain Pulse Width Modulated Output
Characteristic Definitions
Power-On Time When the supply is ramped to its operating
voltage, the device requires a finite time to power its internal
components before supplying a valid PWM output duty-cycle.
Power-On Time, t_PO, is defined as the time it takes for the output
voltage to settle within ±10% of its steady state value after the
power supply has reached its minimum specified operating volt-
age, V_CC(min). (See figure 1.)
Propagation Delay Traveling time of signal from input Hall
plate to output stage of device. (See figure 2.)
Average Quiescent Duty Cycle Output Step Size The
average quiescent duty cycle output step size for a single device
is determined using the following calculation:
Step_{D(Q) =}
D_(Q)(max) – D_(Q)(min)
2ⁿ –1
,
(1)
where:
n is the number of available programming bits in the trim range,
2ⁿ–1 is the value of programming steps in the range,
Response Time The time interval between a) when the applied
magnetic field reaches 90% of its final value, and b) when the
sensor IC reaches 90% of its output corresponding to the applied
magnetic field. (See figure 2.)
D_(Q)(max) is the maximum reached quiescent duty cycle, and
D_(Q)(min) is minimum reached quiescent duty cycle.
PWM Rise Time The time elapsed between 10% and 90% of
the rising signal value when output switches from low to high
states.
0.5 ms
Applied Magnetic
Field, B
PWM Fall Time The time elapsed between 90% and 10% of the
falling signal value when output switches from high to low states.
Time
Quiescent Duty Cycle In the quiescent state (no significant
magnetic field: B = 0 G), the output duty cycle, D_(Q), equals a
specific programmed duty cycle throughout the entire operating
ranges of V_CC and ambient temperature, T_A.
Guaranteed Quiescent Duty Cycle Output Range The
Quiescent Duty Cycle Output, D_(Q), can be programmed around
its nominal value of 50% D, within the Guaranteed Quiescent
Duty Cycle Range limits: D_(Q)(min) and D_(Q)(max). The available
guaranteed programming range for D_(Q) falls within the distribu-
tions of the minimum and the maximum programming code for
setting D_(Q). (See figure 3.)
Propagation
Delay
Response
Time
Output
Figure 2. Definitions of Propagation Delay and Response Time
V+
V_CC(min)
First valid duty cycle
t_PO
V_CC
A1356
Output
Time
Guaranteed D_(Q)
Programming
Range
Min Code D_(Q)
Distribution
D_(Q)(min)
Initial D_(Q)
Distribution
Max Code D_(Q)
Distribution
D_(Q)(max)
Figure 1. Definition of Power-On Time
Figure 3. Definition of Guaranteed Quiescent Voltage Output Range
Allegro MicroSystems, Inc.
8
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com