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5829 Datasheet, PDF (6/12 Pages) Allegro MicroSystems – 9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
5829
9-BIT SERIAL-INPUT,
LATCHED SINK DRIVER
D
CLOCK
A
B
DATA IN
STROBE
E
F
C
HIGH-SIDE
DRIVER OUT
LOAD
CURRENT
G
H
TO I OUT(asym)
I OUT(P) I TRIP
td
t on
t off
Dwg. WP-011A
TIMING CONDITIONS
TA = +25°C, Logic Levels are VDD and Ground
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 500 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
G. Enable Timeout, tEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REN CEN
H. Chop Period*, ton + toff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 RC CC
* Chopping is disabled if VREF is greater than 4.5 V.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000