3968 Datasheet, PDF (6/12 Pages) Allegro MicroSystems – DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE

3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
FUNCTIONAL DESCRIPTION (continued)
Load Current Regulation. Due to internal logic and
switching delays (t_d), the actual load current peak may be
slightly higher than the I_TRIP value. These delays, plus the
blanking time, limit the minimum value the current control
circuitry can regulate. To produce zero current in a
winding, the INPUT_A and INPUT_B terminals should be
held high, turning off all output drivers for that H-bridge.
Output Drivers. To minimize on-chip power dissipa-
tion, the sink drivers incorporate a Satlington™ structure.
The Satlington output combines the low V_CE(sat) features
of a saturated transistor and the high peak-current capa-
bility of a Darlington (connected) transistor. A graph
showing typical output saturation voltages as a function
of output current is on the next page.
Logic Inputs. The direction of current in the motor
winding is determined by the state of the INPUT_A and
INPUT_B terminals of each bridge (see Truth Table). An
internally generated dead time (t_codt) of approximately
1.8 µs prevents cross-over current spikes that can occur
when switching the motor direction.
A logic high on both INPUTs turns off all four output
drivers of that H-bridge. This results in a fast current
decay through the internal ground clamp and flyback
diodes.
The appropriate INPUT_A or INPUT_B can be pulse-
width modulated for applications that require a fast cur-
rent-decay PWM. The internal current-control logic can be
disabled by connecting the R_TC_T terminal to ground.
A logic low on the INPUT_A and the INPUT_B terminals
will place that H-Bridge in the brake mode. Both source
drivers are turned OFF and both sink drivers are turned
ON. This has the effect of shorting the dc motor’s back-
EMF voltage, resulting in a current flow that dynamically
brakes the motor.
Note that during braking the internal current-control
circuitry is disabled. Therefore, care should be taken to
ensure that the motor’s current does not exceed the abso-
lute maximum rating of the A3968.
The REFERENCE input voltage is typically set with a
resistor divider from V_CC. This reference voltage is
internally divided down by 4 to set up the current-com-
parator trip-voltage threshold. The reference input voltage
range is 0 to 2 V.
Miscellaneous Information. Thermal protection
circuitry turns off all output drivers should the junction
temperature reach +165 °C (typical). This is intended
only to protect the device from failures due to excessive
junction temperatures and should not imply that output
short circuits are permitted. Normal operation is resumed
when the junction temperature has decreased about 15 °C.
The A3968 current control employs a fixed-fre-
quency, variable duty cycle PWM technique. If the duty
cycle exceeds 50%, the current-control-regulation fre-
quency may change.
To minimize current-sensing inaccuracies caused by
ground trace I_R drops, each current-sensing resistor
should have a separate return to the ground terminal of
the device. For low-value sense resistors, the I•R drops
in the printed-wiring board can be significant and should
be taken into account. The use of sockets should be
avoided as their contact resistance can cause variations in
the effective value of R_S.
The LOAD SUPPLY terminal, V_BB, should be
decoupled with an electrolytic capacitor (47 µF recom-
mended) placed as close to the device as physically
practical. To minimize the effect of system ground IR
drops on the logic and reference input signals, the system
ground should have a low-resistance return to the load
supply voltage.
The frequency of the clock oscillator will determine
the amount of ripple current. A lower frequency will
result in higher current ripple, but reduced heating in the
motor and driver IC due to a corresponding decrease in
hysteretic core losses and switching losses respectively.
A higher frequency will reduce ripple current, but will
increase switching losses and EMI.
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