A3922 Datasheet, PDF (47/53 Pages) Allegro MicroSystems – Automotive, Full-Bridge MOSFET Driver

A3922
Automotive, Full-Bridge MOSFET Driver
APPLICATION INFORMATION
Power Bridge PWM control
The A3922 provides individual high-side and low-side controls
for each MOSFET drive in the bridge. This allows any full-bridge
control scheme to be implemented by providing four input
control signals. In addition, the sense of the control inputs to
the A3922 are arranged to permit most of the common control
schemes with only one or two control inputs.
When current in a load is only required to be controlled in a
single direction during a specific operation, the most common
control scheme used is slow decay with synchronous rectifica-
tion. This applies two complementary PWM signal to one side
100%
Input Connections
HA
PWM
LAn
0
HBn
DIR
LB
DIR=1
DIR=0
-100%
0%
50%
PWM Duty Cycle
100%
of the bridge, while holding the other side of the bridge with one
MOSFET on and the other off. The control inputs in the A3922
for each side of the bridge are a complementary pair. For phase
A, the high side control input is active high, and the low side is
active-low. This means that the gate drives can be driven in a
complementary mode with a single PWM input signal connected
directly to both high-side and low-side control inputs. A dead
timer is provided for each phase to ensure that current shoot-
through (cross-conduction) is avoided. Figure 8 shows the control
signal connections and the bridge operation for each combination.
The graph shows the approximate effect of the PWM duty cycle
on the average load current for each state of the DIR control
signal. In this case, the current will only flow in one direction for
each state of the DIR signal.
The sense of the control inputs are also complementary for each
phase in a bridge. Phase A, high-side control input is active-high,
while phase B high-side control input is active-low. This means
that it is also possible to drive each bridge in fast decay mode
(4-quadrant control) with a single PWM input signal, as shown
in Figure 9. In this case, the single PWM signal can be used to
control the average load current in both positive and negative
directions. 100% duty cycle gives full positive load current, 0%
gives full negative, and 50% gives zero average load current.
100%
PWM
DIR=1
GHA
GHB GHA
Input Connections
HA
LAn
0
PWM
GHB
HBn
LOAD
LOAD
LB
GLA
GLB
GLA
GLB
PWM
DIR=0
HA=LAn=PWM
HBn=LB=DIR=1
PWM
-100%
0%
50%
PWM Duty Cycle
100%
GHA
GLA
LOAD
GHB GHA
GLB
GLA
LOAD
GHB
GLB
HA=LAn=PWM
HBn=LB=DIR=0
Figure 8: PWM and DIR Inputs, Slow Decay, SR
GHA
GLA
LOAD
GHB GHA
GLB
GLA
LOAD
GHB
GLB
HA=LAn=PWM HBn=LB=DIR
Figure 9: Single PWM Input, Fast Decay, SR
Allegro MicroSystems, LLC
47
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com