A3922 Datasheet, PDF (29/53 Pages) Allegro MicroSystems – Automotive, Full-Bridge MOSFET Driver

A3922
Automotive, Full-Bridge MOSFET Driver
V_BRO = (n + 1) × 2 V
where n is a positive integer defined by VTB[1:0] giving thresh-
olds at 2 V, 4 V, 6 V, and 8 V.
If V_BB – V_BRG exceeds the VBRG open threshold voltage, then
the VBR bit will be set in the verification result register, and
all high-side VDS fault bits will be set in the Diag 1 register.
If ESF = 1, then all gate drive outputs will be disabled. When
V_BB – V_BRG falls below the falling VBRG open threshold voltage
(V_BRO – V_BROHys), the fault state will be reset, and the outputs
will be reactivated. The VBR bit remains in the verification result
register until cleared, and the VDS diagnostic bits remain in the
Diag 1 register until cleared.
Note that, for accurate VBRG disconnect detection at V_BB less
than 12 V, it is important to ensure the selected VBRG disconnect
threshold (V_BRO) is no more than 4 V less than V_BB.
BRIDGE: PHASE STATE MONITOR
The bridge phase connections at the SA and SB terminals are
connected to a variable threshold comparator. The output of the
comparator is stored in the SAS and SBS phase state bits in the
verification result register to provide a logic level monitor of the
state of the power bridge outputs to the load. The threshold for
the two comparators (V_PT) is generated as a ratio of the bridge
voltage by a 6-bit DAC and determined by the contents of the
VPT[5:0] variable.
V_PT is approximately defined as:
n
V= V
64 ^PT
BRG
where n is a positive integer defined by VPT[5:0].
V_PT can be programmed between 0 and 98.4%V_BRG.
SENSE AMPLIFIER DISCONNECT
The sense amplifier includes continuous current sources (I_SAD)
that will allow detection of an input open circuit condition. If an
input open circuit is detected, then the SAD bit will be set in the
verification result register.
BRIDGE: LSS DISCONNECTED
The LSS terminal includes a continuous current source (I_LU) to
V_REG that will pull the LSS terminal up, if there is no low-imped-
ance path from LSS to ground. If the voltage at the LSS terminal
V_BRO
V_DSTH
V_DSTL
V_LSO
V_SAD
V_SAD
VBB
VBAT
VBRG
I_VBRG
Cx
GHx
C_BOOTx
I_SU
R_GH
Sx
I_SD
I_LU
GLx
R_GL
LSSx
I_SAD
CSP
I_SAD
CSM
GND
Figure 7: Bridge Terminal Connection Verification
with respect to ground rises above the LSS open threshold
(V_LSO), then both LSD bits will be set in the Verify Result 0 reg-
ister, and the low-side VDS fault bits (ALO and BLO) will be set
in the Diag 1 register. If ESF = 1, then all gate drive outputs will
be disabled. When the voltage at the LSS terminal falls below the
falling LSS open threshold voltage (V_LSO – V_LSOHys), the fault
state will be reset, and the outputs will be reactivated. The LSD
bits remain in the Verify Result 0 register until cleared, and the
ALO and BLO bits remain in the Diag 1 register until cleared.
Allegro MicroSystems, LLC
29
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com