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| 5910 Datasheet, PDF (4/8 Pages) Allegro MicroSystems – HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS | |||
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5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
CLOCK
DATA IN
STROBE
A
D
B
E
F
C
BLANKING
G
OUTN
Dwg. No. A-12,649A
TIMING CONDITIONS
(TA = +25°C, VDD = 12 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ........................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................... 75 ns
C. Minimum Data Pulse Width ............................................................. 150 ns
D. Minimum Clock Pulse Width ........................................................... 100 ns
E. Minimum Time Between Clock Activation and Strobe .................... 300 ns
F. Minimum Strobe Pulse Width .......................................................... 100 ns
G. Typical Time Between Strobe Activation and
Output Transition ............................................................................. 750 ns
Serial Data present at the input is transferred
to the shift register on the logic â0â to logic â1â
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON. The information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
Output Contents
I1 I2 I3 ... IN-1 IN Blanking I1 I2 I3 ... IN-1 IN
H
H R1 R2 ... RN-2 RN-1 RN-1
L
L R1 R2 ... RN-2 RN-1 RN-1
X
R1 R2 R3 ... RN-1 RN
RN
X X X ... X X
X
L
R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
H
P1 P2 P3 ... PN-1 PN
L
X X X ... X X
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
P1 P2 P3 ... PN-1 PN
L L L ... L L
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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