5821AND Datasheet, PDF (4/8 Pages) Allegro MicroSystems – BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS

5821 AND 5822
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
CLOCK
DATA IN
STROBE
A
D
B
E
F
C
OUTPUT
ENABLE
G
OUT_N
Dwg. No. A-12,627
TIMING CONDITIONS
(V_DD = 5.0 V, T_A = +25°C, Logic Levels are V_DD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ....................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ........................................................................... 75 ns
C. Minimum Data Pulse Width .............................................................. 150 ns
D. Minimum Clock Pulse Width ............................................................ 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 30 ns
F. Minimum Strobe Pulse Width ........................................................... 100 ns
G. Typical Time Between Strobe Activation and
Output Transition .......................................................................... 1.0 µs
Serial Data present at the input is
transferred to the shift register on the
logic “0” to logic “1” transition of the
CLOCK input pulse. On succeeding
CLOCK pulses, the registers shift data
information towards the SERIAL DATA
OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel con-
version). The latches will continue to
accept new data as long as the STROBE
is held high. Applications where the
latches are bypassed (STROBE tied high)
will require that the ENABLE input be
high during serial data entry.
When the ENABLE input is high, all
of the output buffers are disabled (OFF)
without affecting the information stored
in the latches or shift register. With the
ENABLE input low, the outputs are
controlled by the state of the latches.
Serial
Shift Register Contents
Data Clock
Input Input I₁ I₂ I₃ .............. I₈
TRUTH TABLE
Serial
Latch Contents
Data Strobe
Output Input I₁ I₂ I₃ .............. I₈
Output
Enable
Output Contents
I₁ I₂ I₃ .............. I₈
H
H R₁ R₂ .............. R₇
R₇
L
L R₁ R₂ .............. R₇
R₇
X
R₁ R₂ R₃ .............. R₈
R₈
X X X .............. X
X
L
R₁ R₂ R₃ .............. R₈
P₁ P₂ P₃ .............. P₈
P₈
H
P₁ P₂ P₃ .............. P₈
L
P₁ P₂ P₃ .............. P₈
X X X .............. X
H
H H H .............. H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
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