5821AND Datasheet, PDF (2/8 Pages) Allegro MicroSystems – BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS

5821 AND 5822
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TYPICAL INPUT CIRCUITS
VDD
IN
STROBE &
OUTPUT
ENABLE
CLOCK &
SERIAL
DATA IN
IN
Dwg. EP-010-3
VDD
Dwg. EP-010-4A
FUNCTIONAL BLOCK DIAGRAM
CLOCK 1
SERIAL
DATA IN
2
LOGIC
GROUND ³
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V_DD
4 ^LOGIC
SUPPLY
5
SERIAL
DATA OUT
6 _STROBE
7
OUTPUT ENABLE
(ACTIVE LOW)
MOS
BIPOLAR
16
15
14
13
12
11
10
9
OUT ₁ OUT ₂ OUT ₃ OUT ₄ OUT ₅ OUT ₆ OUT ₇ OUT ₈
SUB
POWER
8 _GROUND
Dwg. FP-013A
NOTE — There is an indeterminate resistance between logic ground and power
ground. For proper operation, these terminals must be externally connected
together.
Number of Outputs ON UCN5821A Max. Allowable Duty Cycle
(I_OUT = 200 mA
V_DD = 12 V)
at Ambient Temperature of
25°C 40°C 50°C 60°C 70°C
8
90% 79% 72% 65% 57%
7
100% 90% 82% 74% 65%
6
100% 100% 96% 86% 76%
5
100% 100% 100% 100% 91%
4
100% 100% 100% 100% 100%
3
100% 100% 100% 100% 100%
2
100% 100% 100% 100% 100%
1
100% 100% 100% 100% 100%
TYPICAL OUTPUT DRIVER
OUT
7.2K
3K
SUB
Dwg. No. A-14,314
Number of Outputs ON UCN5821LW Max. Allowable Duty Cycle
(I_OUT = 200 mA
V_DD = 12 V)
at Ambient Temperature of
25°C 40°C 50°C 60°C 70°C
8
67% 59% 54% 49% 43%
7
77% 68% 62% 56% 49%
6
90% 79% 72% 65% 57%
5
100% 95% 86% 78% 68%
4
100% 100% 100% 98% 86%
3
100% 100% 100% 100% 100%
2
100% 100% 100% 100% 100%
1
100% 100% 100% 100% 100%
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