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| 5812-F Datasheet, PDF (4/8 Pages) Allegro MicroSystems – BiMOS II 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS | |||
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5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
CLOCK
DATA IN
STROBE
A
D
B
E
F
C
BLANKING
G
OUTN
Dwg. No. 12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
Serial Data present at the input is transferred
to the shift register on the logic â0â to logic â1â
transition of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The latches
will continue to accept
new data as long as the STROBE is held high.
Applications where the latches are bypassed
(STROBE tied high) will require that the
BLANKING input be high during serial data
entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
TRUTH TABLE
Serial
Data Clock
Input Input
Shift Register Contents
I1 I2 I3 ⦠IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
I1 I2 I3 ⦠IN-1 IN Blanking
H
H R1 R2 ⦠RN-2 RN-1 RN-1
L
L R1 R2 ⦠RN-2 RN-1 RN-1
X
R1 R2 R3 ⦠RN-1 RN
RN
X X X â¦X X
X
L
R1 R2 R3 ⦠RN-1 RN
P1 P2 P3 ⦠PN-1 PN
PN
H
P1 P2 P3 ⦠PN-1 PN
L
X X X â¦X X
H
L = Low Logic Level H = High Logic Level X = Irrelevant
P = Present State R = Previous State
Output Contents
I1 I2 I3 ⦠IN-1 IN
P1 P2 P3 ⦠PN1 PN
L L L â¦L L
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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