A3924 Datasheet, PDF (39/55 Pages) Allegro MicroSystems – Automotive, Full-Bridge MOSFET Driver

A3924
Automotive, Full-Bridge MOSFET Driver
SERIAL REGISTER INTERFACE
Serial Register Reference*
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0: Config 0
TOC3 TOC2 TOC1 TOC0 DT5 DT4 DT3 DT2 DT1 DT0
0
0
0
0
WR
P
1
1
1
1
1
0
0
0
0
0
1: Config 1
OCT3 OCT2 OCT1 OCT0 VTL5 VTL4 VTL3 VTL2 VTL1 VTL0
0
0
0
1
WR
P
1
0
0
1
0
1
1
0
0
0
* Power-on-reset value shown below each input register bit.
Config 0
Config 1
TOC[3:0] – OVERCURRENT VERIFICATION TIME
OCT[3:0] – OVERCURRENT THRESHOLD
t_OCQ = n × 500 ns
where n is a positive integer defined by TOC[3:0]. For example,
for the power-on-reset condition TOC[3:0] = [1111], then t_OCQ =
7.5 µs.
V_OCT = (n + 1) × 300 mV
where n is a positive integer defined by OCT[3:0]. For example,
for the power-on-reset condition OCT[3:0] = [1001], then V_OCT =
3 V.
The range of t_OCQ is 0 to 7.5 µs.
DT[5:0] – DEAD TIME
The range of V_OCT is 0.3 to 4.8 V.
VTL[5:0] – LOW-SIDE VDS OVERVOLTAGE THRESHOLD
t_DEAD = n × 50 ns
where n is a positive integer defined by DT[5:0]. For example,
for the power-on-reset condition DT[5:0] = [10 0000], then t_DEAD
= 1.6 µs.
The range of t_DEAD is 100 ns to 3.15 µs. Selecting a value of 1
or 2 will set the dead time to 100 ns. A value of zero disables the
dead time.
P – PARITY BIT
Ensures an odd number of 1s in any serial transfer.
V_DSTL = n × 50 mV
where n is a positive integer defined by VTL[5:0]. For example,
for the power-on-reset condition VTL[5:0] = [01 1000], then
V_DSTL = 1.2 V.
The range of V_DSTL is 0 to 3.15 V.
P – PARITY BIT
Ensures an odd number of 1s in any serial transfer.
Allegro MicroSystems, LLC
39
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com