A3924 Datasheet, PDF (27/55 Pages) Allegro MicroSystems – Automotive, Full-Bridge MOSFET Driver

A3924
Automotive, Full-Bridge MOSFET Driver
drain-source overvoltage threshold. There are two thresholds:
V_DSTH for the high-side MOSFETs, and V_DSTL for the low-side.
V_DSTH and V_DSTL are generated by internal DACs and are
defined by the values in the VTH[5:0] and VTL[5:0] variables
respectively. These variables provide the input to two 6-bit DACs
with a least significant bit value of typically 50 mV. The output of
the DAC produces the threshold voltage approximately defined
as:
V_DSTH = n × 50 mV
where n is a positive integer defined by VTH[5:0], or:
V_DSTL = n × 50 mV
where n is a positive integer defined by VTL[5:0].
The drain-source voltage for any low-side MOSFET is measured
between the adjacent Sx terminal and the LSS terminal. Using the
LSS terminal rather than the ground connection avoids adding
any low-side current sense voltage to the real low-side drain-
source voltage and avoids false VDS fault detection.
The drain-source voltage for any high-side MOSFET is measured
between the adjacent Sx terminal and the VBRG terminal. Using
the VBRG terminal rather than the VBB avoids adding any
reverse diode voltage or high-side current sense voltage to the
real high-side drain-source voltage and avoids false VDS fault
detection.
The VBRG terminal is an independent low-current sense input to
the top of the MOSFET bridge. It should be connected indepen-
dently and directly to the common connection point for the drains
of the power bridge MOSFETs at the positive supply connection
point in the bridge. The input current to the VBRG terminal is
proportional to the drain-source threshold voltage (V_DSTH), and is
approximately:
I_VBRG = 11 × V_DSTH + 160
where I_VBRG is the current into the VBRG terminal in µA, and
V_DSTH is the drain-source threshold voltage described above.
Note that the VBRG terminal can withstand a negative voltage
up to –5 V. This allows the terminal to remain connected directly
to the top of the power bridge during negative transients, where
the body diodes of the power MOSFETs are used to clamp the
negative transient. The same applies to the more extreme case,
where the MOSFET body diodes are used to clamp a reverse
battery connection.
The output from each VDS overvoltage comparator is filtered by
a VDS fault qualifier circuit. This circuit uses a timer to verify
that the output from the comparator is indicating a valid VDS
fault. The duration of the VDS fault qualifying timer (t_VDQ) is
determined by the contents of the TVD[5:0] variable. t_VDQ is
approximately defined as:
t_VDQ = n × 100 ns
where n is a positive integer defined by TVD[5:0]
The qualifier can operate in one of two ways: debounce mode, or
blanking mode, selected by the VDQ bit.
In the default debounce mode, a timer is started each time the
comparator output indicates a VDS fault detection when the
corresponding MOSFET is active. This timer is reset when the
comparator changes back to indicate normal operation. If the
debounce timer reaches the end of the timeout period, set by
t_VDQ, then the VDS fault is considered valid, and the correspond-
ing VDS fault bit (ALO, AHO, BLO, or BHO) will be set in the
diagnostic register.
In the optional blanking mode, a timer is started when a gate
drive is turned on. The output from the VDS overvoltage com-
parator for the MOSFET being switched on is ignored (blanked)
for the duration of the timeout period, set by t_VDQ. If the com-
parator output indicates an overcurrent event when the MOSFET
is switched on, and the blanking timer is not active, then the VFS
fault is considered valid, and the corresponding VDS fault bit
(ALO, AHO, BLO, or BHO) will be set in the Diag 1 register.
The action taken when a valid VDS fault is detected and the fault
reset conditions depend on the state of the ESF bit.
If ESF = 0 the fault state will be latched, the general fault flag
will be active, the associated VDS fault bit will be set, and the
associated MOSFET will be disabled. The fault state and the
general fault flag will be reset by a low pulse on the RESETn
input, by a serial read of the Diag 1 register, by a power-on reset
or the next time the MOSFET is commanded to switch on. If the
MOSFET is being driven with a PWM signal, then this will usu-
ally mean that the MOSFET will be turned on again each PWM
cycle. If this is the case, and the fault conditions remains, then a
valid fault will again be detected after the timeout period and the
sequence will repeat. In this case, the general fault flag will only
be reset for the duration of the validation timer. The VDS fault bit
will only be cleared by a serial read of the Diag 1 register or by a
power-on reset.
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