A4910 Datasheet, PDF (34/36 Pages) Allegro MicroSystems – Automotive 3-Phase MOSFET Driver

A4910
Automotive 3-Phase MOSFET Driver
Layout Recommendations
Careful consideration must be given to PCB layout when design-
ing high frequency, fast-switching, high-current circuits:
• The A4910 analog ground, AGND, and power ground, PGND,
should be connected together at the package terminals. This
common point should return separately to the negative side of the
motor supply filtering capacitor. This will minimize the effect of
switching noise on the device logic and analog reference.
• The exposed thermal pad should be connected to the common
point of AGND and PGND.
• Minimize stray inductance by using short, wide copper traces
at the drain and source terminals of all power MOSFETs. This
includes motor lead connections, the input power bus, and the
common source of the low-side power MOSFETs. This will mini-
mize voltages induced by fast switching of large load currents.
• Consider the addition of small (100 nF) ceramic decoupling
capacitors across the source and drain of the power MOSFETs to
limit fast transient voltage spikes caused by PCB trace induc-
tance.
• Keep the gate discharge return connections Sx and LSSx as
short as possible. Any inductance on these traces will cause nega-
tive transitions on the corresponding A4910 terminals, which may
exceed the absolute maximum ratings. If this is likely, consider
the use of clamping diodes to limit the negative excursion on
these terminals with respect to AGND.
• Supply decoupling for VBB, VREG and VDD should be con-
nected independently, close to the PGND terminal. The decou-
pling capacitors should also be connected as close as possible to
the relevant supply terminal.
• Check the peak voltage excursion of the transients on the
LSSx terminals with reference to the AGND terminal using a
close-grounded (tip and barrel) probe. If the voltage at any LSSx
terminal exceeds the absolute maximum in the datasheet, add
additional clamping and/or capacitance between the LSSx termi-
nal and the AGND terminal.
• Gate charge drive paths and gate discharge return paths may
carry a large transient current pulse. Therefore the traces from
GHx, GLx, Sx and LSSx (x = A, B or C) should be as short as
possible to reduce inductance in the traces.
• Provide an independent connection from each LSSx terminal to
the source of the corresponding low-side MOSFET in the power
bridge. Connection of the LSSx terminals directly to the PGND
terminal is not recommended as this may inject noise into sensi-
tive functions such as the various voltage monitors.
• The inputs to the sense amplifiers, CSxP and CSxM, should
take the form of independent traces and for best results should be
matched in length and route.
• A low cost diode can be placed in the connection to VBB to
provide reverse battery protection. In reverse battery conditions
it is possible to use the body diodes of the power MOSFETs to
clamp the reverse voltage to approximately 4 V. In this case the
additional diode in the VBB connection will prevent damage to
the A4910 and the VBRG input will survive the reverse voltage.
Optional reverse battery protection
VBB _VBRG
VREG
GHC
GHB
GHA
VDD
SA
SB
A4910 ^SC
GLA
GLB
GLC
LSSA
LSSB
LSSC
AGND PGND
R_S
Controller Supply Ground
Figure 13. Supply Routing Suggestions
R_S
R_S
Power Ground
+ Supply
Motor
Supply
Common
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