A4910 Datasheet, PDF (22/36 Pages) Allegro MicroSystems – Automotive 3-Phase MOSFET Driver

A4910
Automotive 3-Phase MOSFET Driver
avoids adding any low-side current sense voltage to the real
low-side drain-source voltage. The high-side drain-source voltage
for any MOSFET is measured between the VBRG terminal and
the appropriate Sx terminal. Using the VBRG terminal rather
than the bridge supply avoids adding any high-side current sense
voltage to the real high-side drain-source voltage.
VBRG is a low-current input allowing a voltage sense connec-
tion to be made with the top of the external MOSFET bridge. It
should be connected directly to the common connection point for
the drains of the power bridge MOSFETs at the positive sup-
ply connection point. The input current to the VBRG terminal is
proportional to the drain-source threshold voltage, VDSTH, and
can be approximated by:
I_VBRG = 72 × V_DSTH + 52
(2)
where I_VBRG is the current into the VBRG terminal in μA and
V_DSTH is the voltage on the V_DSTH terminal in V.
Fault Blanking Time To avoid false MOSFET fault detection
during switching transients, the V_DS to V_DSTH comparison is
delayed by an internal fault blanking timer. The fault blanking
time is defined by the contents of the BT[5..0] bits in the Config0
register. These bits provide the input to a 6-bit counter that is
clocked by a divide-by-four clock derived from the system clock
(typically 20 MHz).
Short Fault Operation As the phase switches, the measured
drain-source voltage may generate a fault because power
MOSFETs take a finite time to reach their rated on-resistance. To
overcome this and avoid generating false short faults, the volt-
ages are not sampled until one fault blanking time period after
the external MOSFET is turned on. If the drain-source voltage
remains above the threshold after the fault blanking time expires,
then a short fault will be generated. If the ESF bit in the Config1
register is set to 1, this fault will be latched and the MOSFET
disabled until reset.
In some applications it may be necessary to increase the switch-
ing time of the external MOSFET by increasing the value of the
gate resistor. This will mean that the fault blanking time may be
insufficient to avoid generating incorrect fault states. In these
cases, by setting the ESF bit to 0, the microcontroller driving
the A4910 can be used to determine the correct fault condition.
This will disable fault flag latching during a short condition and
the general fault flag, available on the DIAG terminal, will only
remain low while the measured drain-source voltages show a
fault. The microcontroller can then monitor the fault flags and use
its own timers to validate the fault condition. Note that, regard-
less of the ESF setting, any fault detected by the A4910 will still
be latched in the Diagnostic register and remain there until reset.
The fault blanking time is defined as:
t_BL = n × 100 ns
(3)
where n is a positive integer defined by BT[5..0] and 100 ns is
twice the typical system clock period.
For example, when BT[5..0] contains [0 1 1 0 1 0] (26 decimal),
then t_BL is 2.6 μs (typical).
If a short circuit fault occurs and ESF is set to 0, the external
MOSFETs are not disabled by the A4910. To limit any damage
to the external MOSFETs or to the motor, the A4910 can either
be fully disabled by the RESETn input or all MOSFETs can be
switched off by pulling the COASTn input low. Alternatively, set-
ting ESF to 1 allows the A4910 to disable the MOSFETs as soon
as a fault is detected.
Allegro MicroSystems, LLC
22
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com