A4927 Datasheet, PDF (24/40 Pages) Allegro MicroSystems – Automotive Half-Bridge MOSFET Driver

A4927
Automotive Half-Bridge MOSFET Driver
MOSFET FAULT STATE: SHORT TO SUPPLY
A short from the load connections to the battery or VBB connec-
tion is detected by monitoring the voltage across the low-side
MOSFET using the S terminal and the LSS terminal. This drain-
source voltage is then compared to the low-side Drain-Source
Threshold Voltage, V_DSTL. If the blanking timer is active, the
output from the VDS overvoltage comparator will be ignored for
t_VDQ. While the low-side VDS fault is detected, the VDS fault
bit, LO, will be set in the diagnostic register and the low-side
MOSFET will be disabled. When ESF is set to 1, both MOSFETs
will be disabled.
MOSFET FAULT STATE: SHORT TO GROUND
A short from the load connection to ground is detected by
monitoring the voltage across the low-side MOSFET using the S
terminal and the voltage at VBRG. This drain-source voltage is
then compared to the high-side Drain-Source Threshold Volt-
age, V_DSTH. If the blanking timer is active, the output from the
VDS overvoltage comparator will be ignored for t_VDQ. While the
low-side VDS fault is detected, the VDS fault bit, HO, will be
set in the diagnostic register and the high-side MOSFET will be
disabled. When ESF is set to 1, both MOSFETs will be disabled.
Fault Action
The action taken when one of the diagnostic functions indicates a
fault is listed in Table 5.
When a fault is detected, a corresponding fault state is consid-
ered to exist. In some cases, the fault state only exists during the
time the fault is detected. In other cases, when the fault is only
detected for a short time, the fault state is latched (stored) until
reset. The faults that are latched are indicated in Table 5. Latched
fault states are always reset when RESETn is taken low, a power-
on-reset state is present or when the associated fault bit is read
through the serial interface. Any fault bits that have been set in
the status or diagnostic register are only reset when a power-
on-reset state is present or when the associated fault bit is read
through the serial interface. RESETn low will not reset the fault
bits in the status or diagnostic registers.
The fault conditions power-on-reset and VREG undervoltage
are considered critical to the safe operation of the A4927 and the
system. If these faults are detected, then the gate drive outputs are
automatically driven low and both MOSFETs in the bridge held
in the off state. This state will remain until the fault is removed.
For the logic terminal overvoltage and overtemperature fault
conditions, the action taken depends on the status of the ESF bit.
If a fault is detected on any of these two diagnostics and ESF = 1,
then all the gate drive outputs will be driven low and all MOS-
FETs in the bridge held in the off state. This state will remain
until the fault is removed. If ESF = 0, then the gate drive outputs
will not be affected.
If a VDS fault or bootstrap undervoltage fault is detected, then the
action taken will also depend on the status of the ESF bit, but these
faults are handled as a special case. If a fault is detected on any of
these two diagnostics and ESF = 1, then both gate drive outputs
will be driven low and both MOSFETs in the bridge will be held
in the off state. When ESF = 1, this fault state will be latched and
remain until reset. If a VDS fault or bootstrap undervoltage fault
is detected and ESF = 0, then only the gate drive output to the
MOSFET where the fault was detected will be driven low and the
MOSFET will be held in the off state. When ESF = 0, the VDS
fault or bootstrap undervoltage fault state will be latched but will
be reset the next time the MOSFET is commanded to switch on.
For all other faults, the gate drive outputs will remain enabled.
Fault Masks
Individual diagnostics—except power-on reset, serial transmis-
sion error, and overtemperature—can be disabled by setting the
corresponding bit in the mask register. Power-on-reset cannot be
disabled because the diagnostics and the output control depend
on the logic regulator to operate correctly. If a bit is set to one
in the mask register, then the corresponding diagnostic will be
completely disabled. No fault states for the disabled diagnostic
will be generated and no fault flags or diagnostic bits will be set.
See Mask Register definition for bit allocation. Care must be
taken when diagnostics are disabled to avoid potentially damag-
ing conditions.
Table 5: Fault Actions
Fault
Description
No Fault
Power-on-Reset
VREG undervoltage
VREG overvoltage
VBB overvoltage
Overtemperature
Temperature warning
Serial transmission error
Bootstrap undervoltage
Overcurrent
VDS overvoltage
VGS undervoltage
Disable Outputs
ESF = 0 ESF = 1
No
No
Yes ^[1]
Yes ^[1]
Yes ^[1]
Yes ^[1]
No
No
No
No
No
Yes ^[1]
No
No
No
No
Yes ^[2]
Yes ^[1]
No
No
Yes ^[2]
Yes ^[1]
No
No
Fault State
Latched
-
No
No
No
No
No
No
No
Yes
No
Yes
No
1 _{Both gate drives low, both MOSFETs off.}
2 _{Gate drive to the affected MOSFET low, only the affected MOSFET off.}
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