A8650 Datasheet, PDF (22/31 Pages) Allegro MicroSystems – Low Input Voltage, Adjustable Frequency 2 A Synchronous Buck Regulator with EN/SYNC and Power OK

A8650
Low Input Voltage, Adjustable Frequency
2 A Synchronous Buck Regulator with EN/SYNC and Power OK
is higher than the cycle-by-cycle current threshold, as shown in
figure 12. This phenomena is more pronounced when using high
value electrolytic type output capacitors. To avoid prematurely
triggering hiccup mode the soft start capacitor, C_SS , should be
calculated according to:
C_SS ≥
I_{SSSU ×} V_{OUT ×} C_OUT
0.8 (V) _× I_CO
(18)
where V_OUT is the output voltage, C_OUT is the output capacitance,
I_CO is the amount of current allowed to charge the output capaci-
tance during soft start (recommend 0.1 A < I_CO < 0.3 A). Higher
values of I_CO result in faster soft start times. However, lower
values of I_CO ensure that hiccup mode is not falsely triggered.
Allegro recommends starting the design with an I_CO of 0.1 A and
increasing it only if the soft start time is too slow. If a non-stan-
dard capacitor value for C_SS is calculated, the next larger value
should be used.
The output voltage ramp time, t_SS , can be calculated by using
either of the following methods:
or
t_SS = V_{OUT ×}
C_OUT
I_CO
(19)
t_{SS =}
0.8 (V) ×
C_SS
I_SSSU
(20)
When the A8650 is in hiccup mode, the soft start capacitor is
used as a timing capacitor and sets the hiccup period. The soft
start pin charges the soft start capacitor with I_SSSU during a
startup attempt, and discharges the same capacitor with I_SSHIC
between startup attempts. Because the ratio I_SSSU / I_SSHIC is
approximately 2:1, the time between hiccups will be about two
I _LIM
I _LOAD
t _SS
}
Output
capacitor
current, I _CO
Figure 12. Output current (I_CO) during startup
times as long as the startup time. Therefore, the effective duty-
cycle of the A8650 will be very low and the junction temperature
will be kept low.
Compensation Components (R_Z , C_Z , C_P )
To compensate the system it is important to understand where
the buck power stage, load resistance, and output capacitance
form their poles and zeros in frequency. Also, its important to
understand not only that the (Type II) compensated error ampli-
fier introduces a zero and two more poles, but also where these
should be placed to maximize system stability, provide a high
bandwidth, and optimize the transient response.
First, consider the power stage of the A8650, the output capaci-
tors, and the load resistance. This circuitry is commonly referred
as the control-to-output (CO) transfer function. The low fre-
quency gain of this circuitry depends on the COMP to SW current
gain ( g_mPOWER ), and the value of the load resistor (R_L ). The DC
gain (G_CO(0HZ)) of the control-to-output is:
G_CO(0Hz) = g_mPOWER × R_L
(21)
The control-to-output transfer function has a pole (f_P1), formed
by the output capacitance (C_OUT) and load resistance (R_L),
located at:
f_P1 =
2�
×
1
R_L × C_OUT
(22)
The control-to-output transfer function also has a zero (f_Z1)
formed by the output capacitance (C_OUT) and its associated ESR:
f_Z1
=
2�
1
× ESR ×
C_OUT
(23)
For a design with very low-ESR type output capacitors (such as
ceramic capacitors), the ESR zero (f_Z1) is usually at a very high
frequency, so it can be ignored. On the other hand, if the ESR
zero falls below or near the 0 dB crossover frequency of the
system (as is the case with electrolytic output capacitors), then it
should be cancelled by the pole formed by the C_P capacitor and
the R_Z resistor (discussed and identified later as f_P3).
A Bode plot of the control-to-output transfer function for the
A8650 circuit shown in the typical application schematic on the
front page (V_OUT = 1.8 V, I_OUT = 2.0 A, R_L = 0.9 Ω) is shown in
figure 13. The pole at f_P1 can easily be seen at 8.8 kHz while the
ESR zero, f_Z1, occurs at a very high frequency, 4 MHz (this is
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