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A3944 Datasheet, PDF (21/31 Pages) Allegro MicroSystems – Automotive, Low-Side FET Pre-Driver
A3944
Automotive, Low Side FET Pre-Driver
Applications Information
Drain Feedback Clamp Resistor Selection
The drain feedback input, DRNx, for each channel is clamped
internally with a 50 V (nominal) Zener diode. If the voltage
applied to this terminal is likely to exceed 50 V then an external
current limit resistor will be required to limit the current, power,
and energy to less than the Absolute Maximum specifications in
this document.
Note that the internal drain clamp in the A3944 is not intended to
dissipate the energy from any external load. The internal clamp
is provided to protect the internal circuits of the A3944 from any
high voltage that would otherwise cause permanent damage.
If the voltage at DRNx, VDRNx , will never exceed the minimum
drain clamp voltage, VDCL , then no external resistor is required
and DRNx can be connected directly to the drain of the external
MOSFET switch.
Three Absolute Maximum specifications apply to the A3944,
none of which may be exceeded:
• The maximum clamp current, IDRNC , applies to very short
pulses, typically less than 1.85 μs. Any current pulse less than
1.85 μs and less than IDRNC , will never exceed the maximum
power or energy limits.
• The maximum clamp energy, EDRNC , applies to pulses between
1.85 μs and 2 ms. Above 2 ms the heat produced by the clamp
energy dissipates through the silicon and the package; in that
case, the maximum clamp power applies. Note that for pulse
lengths between about 500 μs and 2 ms the energy starts to dis-
sipate during the pulse, so the maximum current that is possible
will actually be higher than that calculated using the maximum
energy limit.
• The maximum clamp power, PDRNC , applies to pulses lasting
longer than 2 ms up to continuous operation.
Maximum current example:
• Load resistance: 26 Ω
• Load inductance: 130 μH
• Load current: 0.5 A
• Load supply voltage: 13 V
• FET clamp voltage: 80 V
These values would typically apply to a remote load which is
primarily resistive. The load inductance will be due to a combina-
tion of the wiring and any parasitic inductance in the load. In this
example, the DC on-state current will be 13 V / 26 Ω = 0.5 A.
When the load is switched off, the inductance attempts to keep
the current flowing by increasing the voltage at the end connect
to the FET switch. This voltage increases up to the breakdown
voltage of the FET. At that point, the voltage across the load
amounts to the difference between the FET breakdown voltage
and the supply voltage, and it acts to reduce the current. With the
parameters in this example, the current would decay to zero in
less than 1 μs. This is less than the 1.85 μs limit for maximum
current, so the drain resistor will be based only on the maximum
current. The value of the drain resistor, RDx , in this case is simply
the voltage across the resistor divided by the maximum current:
RDx =
VFET – VDCL
IDRNC
(1)
where
VFET is the FET breakdown voltage,
VDCL is the A3944 drain clamp voltage, and
IDRNC is the A3944 drain clamp max current.
Substituting into equation 1:
80 V – 54 V
RDx = 100 mA = 260 Ω
The energy injected into the A3944 drain clamp is:
EDRNC = VDCL × IDRNC × tPULSE
(2)
where tPULSE is the duration of the current pulse.
Substituting into equation 2:
EDRNC = 54 V × 100 mA × 0.9 μs = 4.86 μJ (per pulse)
As expected, based on the pulse length, this is less than half the
clamp energy limit, given in the Absolute Maximum table.
Allegro MicroSystems, Inc.
21
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com