A1365 Datasheet, PDF (19/32 Pages) Allegro MicroSystems – Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC

A1365
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
With High-Bandwidth (120 kHz) Analog Output and Integrated Fault Comparator
FUNCTIONAL DESCRIPTION
Programming Sensitivity and Quiescent Volt-
age Output
Sensitivity and V_OUT(Q) can be adjusted by programming
SENS_FINE and QVO bits, as illustrated in Figures 7 and 8.
Users should not program sensitivity or V_OUT(Q) beyond the
maximum or minimum programming ranges specified in the
Operating Characteristics table. Exceeding the specified limits
will cause the sensitivity and V_OUT(Q) drift over the temperature
range (ΔSens_TC and ΔV_{OUT(Q)TC }) to deteriorate beyond the
specified values.
Programming sensitivity might cause a small drift in V_OUT(Q) . As
a result, Allegro recommends programming sensitivity first, then
V_OUT(Q) .
Coarse Sensitivity
Each A1365 variant is programmed to a different coarse sensitiv-
ity setting. Devices are tested, and temperature compensation is
factory-programmed under that specific coarse sensitivity setting.
If the coarse sensitivity setting is changed, by programming
SENS_COARSE bits, Allegro cannot guarantee the specified
sensitivity drift through temperature range limits (ΔSens_TC ).
Memory-Locking Mechanisms
The A1365 is equipped with two distinct memory-locking
mechanisms:
• Default Lock At power-up, all registers of the A1365 are
locked by default. EEPROM and volatile memory cannot be
read or written. To disable Default Lock, a specific 30-bit
customer access code has to be written to address 0x24 within
Access Code Timeout (t_ACC = 8 ms) from power-up. After
doing so, registers can be accessed. If VCC is power-cycled,
the Default Lock will automatically be re-enabled. This
ensures that during normal operation, memory content will not
be altered due to unwanted glitches on VCC or the output pin.
• Lock Bit After EEPROM has been programmed by the user,
the EELOCK bit can be set high and VCC power-cycled to
permanently disable the ability to read or write any register.
This will prevent the ability to disable Default Lock using the
method described above. Note that after the EELOCK bit is
set high and the VCC pin is power-cycled, you will not have
the ability to clear the EELOCK bit or read/write any register.
Sensitivity, Sens (mV/G)
Max Specified
Sens_PR
Mid Range
Specified Sensitivity
Programming Range
Quiescent Voltage Output,
V_OUT(Q) (mV)
Max Specified
V_OUT(Q)PR
Mid Range
Specified V_OUT(Q)
Programming Range
Min Specified
Sens_PR
0
255 256
511
SENS_FINE Code
Figure 9: Device Sensitivity versus SENS_FINE
Programmed Value
Min Specified
V_OUT(Q)PR
0
255 256
511
QVO Code
Figure 10: Device V_OUT(Q) versus QVO
Programmed Value
Allegro MicroSystems, LLC
19
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com