A4982_V4 Datasheet, PDF (17/20 Pages) Allegro MicroSystems – DMOS Microstepping Driver with Translator And Overcurrent Protection

A4982
DMOS Microstepping Driver with Translator
And Overcurrent Protection
ET Package
Pin-out Diagrams
LP Package
OUT2B 1
NC 2
VBB2 3
NC 4
ENABLE 5
GND 6
CP1 7
CP2 8
24 OUT1B
23 NC
22 VBB1
PAD
21 NC
20 DIR
19 GND
18 REF
17 STEP
CP1 1
CP2 2
VCP 3
VREG 4
MS1 5
MS2 6
RESET 7
ROSC 8
SLEEP 9
VDD 10
STEP 11
REF 12
PAD
24 GND
23 ENABLE
22 OUT2B
21 VBB2
20 SENSE2
19 OUT2A
18 OUT1A
17 SENSE1
16 VBB1
15 OUT1B
14 DIR
13 GND
Terminal List Table
Name
Number
ET¹
LP
Description
CP1
7
1
Charge pump capacitor terminal
CP2
8
2
Charge pump capacitor terminal
DIR
¯E¯ ¯N¯ ¯A¯ ¯B¯ ¯L¯ ¯E¯
GND
20
5
6, 19
14
23
13, 24
Logic input
Logic input
Ground²
MS1
11
5
Logic input
MS2
12
6
Logic input
2, 4, 21,
NC
23, 26, 28,
–
No connection
29, 31
OUT1A
27
18
DMOS Full Bridge 1 Output A
OUT1B
24
15
DMOS Full Bridge 1 Output B
OUT2A
30
19
DMOS Full Bridge 2 Output A
OUT2B
1
22
DMOS Full Bridge 2 Output B
REF
18
¯R¯ ¯E¯ ¯S¯ ¯E¯ ¯T¯
13
12
G_m reference voltage input
7
Logic input
ROSC
14
8
Timing set
SENSE1
25
17
Sense resistor terminal for Bridge 1
SENSE2
32
¯S¯ ¯L¯ ¯E¯ ¯E¯ ¯P¯
15
20
Sense resistor terminal for Bridge 2
9
Logic input
STEP
17
11
Logic input
VBB1
22
16
Load supply
VBB2
3
21
Load supply
VCP
9
3
Reservoir capacitor terminal
VDD
16
10
Logic supply
VREG
10
4
Regulator decoupling terminal
PAD
–
–
Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.
Allegro MicroSystems, Inc.
17
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com