A4982_V4 Datasheet, PDF (12/20 Pages) Allegro MicroSystems – DMOS Microstepping Driver with Translator And Overcurrent Protection

A4982
DMOS Microstepping Driver with Translator
And Overcurrent Protection
Application Layout
Layout. Typical application circuits and layouts are shown in
figures 8 (LP package) and 9 (ET package).The printed circuit
board should use a heavy groundplane. For optimum electrical
and thermal performance, the A4982 must be soldered directly
onto the board. On the underside of the A4982 package is an
exposed pad, which provides a path for enhanced thermal dissipa-
tion. The thermal pad should be soldered directly to an exposed
surface on the PCB. Thermal vias are used to transfer heat to
other layers of the PCB.
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance single-point
ground, known as a star ground, located very close to the device.
By making the connection between the pad and the ground plane
directly under the A4982, that area becomes an ideal location for
a star ground point. A low impedance ground will prevent ground
bounce during high current operation and ensure that the supply
voltage remains stable at the input terminal.
The two input capacitors should be placed in parallel, and as
close to the device supply pins as possible. The ceramic capaci-
tor (CIN1) should be closer to the pins than the bulk capacitor
(CIN2). This is necessary because the ceramic capacitor will be
responsible for delivering the high frequency current components.
The sense resistors, RSx , should have a very low impedance
path to ground, because they must carry a large current while
supporting very accurate voltage measurements by the current
sense comparators. Long ground traces will cause additional
voltage drops, adversely affecting the ability of the comparators
to accurately measure the current in the windings. The SENSEx
pins have very short traces to the RSx resistors and very thick,
low impedance traces directly to the star ground underneath the
device. If possible, there should be no other components on the
sense circuits.
A4982
PCB
Thermal Vias
Solder
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
Thermal (2 oz.)
C3
C4
GND
C5
ROSC
C1
GND
GND
VDD
C6
GND
U1
OUT2B
GND
OUT2A
R4
R5
OUT1A
GND
GND
VBB
OUT1B
BULK
CAPACITANCE
C2
GND
C3
C4
C5
ROSC
C1
VDD
CP1
A4982
GND
CP2
VCP
ENABLE
OUT2B
VBB2
VREG
MS1
MS2
RESET
ROSC
SLEEP
VDD
STEP
PAD _SENSE2
OUT2A ^R4
OUT1A
SENSE1
R5
VBB1
OUT1B
DIR
REF
GND
C6
C2
VBB
Figure 8. LP package typical application and circuit layout
Allegro MicroSystems, Inc.
12
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com