ISL3158AE Datasheet, PDF (7/16 Pages) Intersil Corporation – ±16.5kV ESD (IEC61000-4-2) Protected, Large Output Swing, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceiver

ISL3158AE
Electrical Specifications
Test Conditions: V_CC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at V_CC = 5V, T_A = +25°C
(Note 2). Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C) MIN
TYP
MAX UNITS
Receiver Enable to Output High
t_ZH
R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 6), Full
-
(Note 6)
7
15
ns
Receiver Disable from Output Low
t_LZ
R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 6)
Full
-
8
15
ns
Receiver Disable from Output High
t_HZ
R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 6)
Full
-
8
15
ns
Time to Shutdown
t_SHDN (Notes 7, 12)
Full
60
160
600
ns
Receiver Enable from Shutdown to t_ZH(SHDN) R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 6), Full
-
Output High
(Notes 7, 9)
-
200
ns
Receiver Enable from Shutdown to t_ZL(SHDN) R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 6), Full
-
Output Low
(Notes 7, 9)
-
200
ns
NOTES:
2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
3. Supply current specification is valid for loaded drivers when DE = 0V.
4. Applies to peak current. See “Typical Performance Curves” beginning on page 12 for more information.
5. Keep RE = 0 to prevent the device from entering SHDN.
6. The RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.
7. Transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts are guaranteed
not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See “Low Power
Shutdown Mode” on page 11.
8. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.
9. Set the RE signal high time >600ns to ensure that the device enters SHDN.
10. See Figure 8 for more information, and for performance over-temperature.
11. For wafer sale, the switching test limits are established by characterization.
12. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
V_CC ^DE
DI
Z
D
Y
V_OD
R_L/2
R_L/2 VOC
V_CC ^DE
DI
Z
D
Y
V_OD
375Ω
R_L = 60Ω
V_CM
-7V TO +12V
375Ω
FIGURE 1A. V_OD AND V_OC
FIGURE 1B. V_OD WITH COMMON MODE LOAD
FIGURE 1. DC DRIVER TEST CIRCUITS
7
FN6886.0
April 3, 2009