AK5380 Datasheet, PDF (9/17 Pages) Asahi Kasei Microsystems – 96kHz 24Bit ADC with Single - ended Input

ASAHI KASEI
[AK5380]
SWITCHING CHARACTERISTICS (fs=48kHz∼96kHz)
(Ta=-40∼85°C; VA=4.5∼5.5V; VD=4.5∼5.5V; C_L=20pF)
Parameter
Symbol
min
typ
Control Clock Frequency
Master Clock 256fs:
fCLK
12.288
Pulse Width Low
tCLKL
16
Pulse Width High
tCLKH
16
384fs:
fCLK
18.432
Pulse Width Low
fCLKL
11
Pulse Width High
fCLKH
11
SCLK Frequency
fSLK
LRCK Frequency
fs
48
Serial Interface Timing
(Note 12)
SCLK Period
tSLK
160
SCLK Pulse Width Low
tSLKL
65
Pulse Width High
tSLKH
65
LRCK Edge to SCLK “↑” (Note 13)
tLRSH
30
SCLK “↑” to LRCK Edge (Note 13)
tSHLR
30
LRCK Edge to SDTO Valid (Note 14)
tDLR
SCLK “↓” to SDTO Valid
tDSS
Power-Down & Reset Timing
PDN Pulse Width
tPDW
150
PDN “↑” to SDTO delay
(Note 15) tPDV
4129
Notes:
12. Refer to the operating overview section “Serial Data Interface”.
13. SCLK rising edge must not occur at the same time as LRCK edge.
14. In case of MSB justified format.
15. These cycles are the number of LRCK rising from PDN rising.
max
24.576
36.864
6.144
96
20
20
Units
MHz
ns
ns
MHz
ns
ns
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
MS0100-E-01
-9-
2001/7