AK5380 Datasheet, PDF (11/17 Pages) Asahi Kasei Microsystems – 96kHz 24Bit ADC with Single - ended Input

ASAHI KASEI
[AK5380]
OPERATION OVERVIEW
n System Clock Input
The external clocks which are required to operate the AK5380 are MCLK(256fs/384fs/512fs/768fs), LRCK(1fs), SCLK.
MCLK should be synchronized with LRCK but the phase is not critical. When 384fs, 512fs or 768fs clock is input to
MCLK pin, the internal master clock becomes 256fs(=384fs x 2/3=512fs x 1/2=768fs x 1/3). Table 1 illustrates standard
audio word rates and corresponding frequencies used in the AK5380.
All external clocks (MCLK,BICK,LRCK) should always be present whenever the AK5380 is in normal operation mode
(PDN = “H”). If these clocks are not provided, the AK5380 may draw excess current and may not possibly operate
properly because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK5380
should be in the power-down mode (PDN = “L”). After exiting reset at power-up etc., the AK5380 is in the power-down
mode until MCLK and LRCK are input.
fs
32.0kHz
44.1kHz
48.0kHz
96.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
24.5760MHz
MCLK
384fs
512fs
12.2880MHz 16.3840MHz
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
36.8640MHz
N/A
768fs
24.576MHz
33.8688MHz
36.8640MHz
N/A
SCLK
64fs
128fs
2.0480MHz 4.0960MHz
2.8224MHz 5.6448MHz
3.0720MHz 6.1440MHz
6.1440MHz
N/A
Table 1. Example of System Clock
n Serial Data Interface
Two kinds of data format can be selected by DIF pin. The data is clocked out via the SDTO pin by SCLK corresponding
to the setting of DIF pin. The format of output data is 2’s complement MSB first.
Mode
0
1
DIF
Format
0
24bit, MSB justified, L/R, SCLK ≥48fs (16bit, MSB justified, L/R, SCLK=32fs)
1
24bit, I2S,
SCLK ≥48fs (16bit, I2S,
SCLK=32fs)
Table 2. Audio Serial Interface Formats
MS0100-E-01
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