AK5353 Datasheet, PDF (9/17 Pages) Asahi Kasei Microsystems – 96kHz 24BIT ADC WITH SIGLE-ENDED INPUT

ASAHI KASEI
[AK5353]
SWITCHING CHARACTERISTICS (VA,VD=2.7∼4.5V)
(Ta=25°C; VA,VD=2.7∼4.5V; C_L=20pF)
Parameter
Symbol
min
typ
Control Clock Frequency
Master Clock 256fs:
fCLK
1.024
Pulse Width Low
tCLKL
32
Pulse Width High
tCLKH
32
384fs:
fCLK
1.536
Pulse Width Low
fCLKL
21
Pulse Width High
fCLKH
21
512fs:
fCLK
2.048
Pulse Width Low
fCLKL
16
Pulse Width High
fCLKH
16
SCLK Frequency
fSLK
LRCK Frequency
fs
4
Serial Interface Timing
(Note 12)
SCLK Period
tSLK
160
SCLK Pulse Width Low
tSLKL
65
Pulse Width High
tSLKH
65
LRCK Edge to SCLK ↑
(Note 13) tLRSH
30
SCLK ↑ to LRCK Edge
(Note 13)
tSHLR
30
LRCK Edge to SDTO Valid (Note 14) ^tDLR
SCLK ↓ to SDTO Valid
tDSS
Power-Down & Reset Timing
PDN Pulse Width
tPDW
150
PDN ↓ to SDTO delay
(Note 15) tPDV
4129
Note:12. Refer to the operating overview section Serial Data Interface .
13. SCLK rising edge must not occur at the same time as LRCK edge.
14. In case of MSB justified format.
15. These cycles are the number of LRCK rising from PDN falling.
max
12.288
18.432
24.576
6.144
48
50
50
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
M0067-E-00
-9-
1999/06