AK5353 Datasheet, PDF (13/17 Pages) Asahi Kasei Microsystems – 96kHz 24BIT ADC WITH SIGLE-ENDED INPUT

ASAHI KASEI
[AK5353]
n Power down
The AK5353 is placed in the power-down mode by bringing PDN L and the digital filter is also reset at the same time.
This reset should always be done after power-up. In the power-down mode, the VREF and VCOM are AGND level. An
analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available
after 4129 cycles of LRCK clock. During initialization, the ADC digital data outputs of both channels are forced to a 2 s
complement 0 . The ADC outputs settle in the data corresponding to the input signals after the end of initialization
(Settling approximately takes the group delay time).
PDN
Internal
State
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
4129/fs(86.021ms@fs=48kHz)
Normal Operation
GD ₍₁₎
Power-down
Idle Noise
(2)
0 data
(3)
Initialize
Normal Operation
GD
0 data
Idle Noise
Notes:
(1) Digital output corresponding to analog input has the group delay (GD).
(2) A/D output is 0 data at the power-down state.
(3) When the external clocks (MCLK,SCLK,LRCK) are stopped, the AK5353 should be in the power-down state.
Figure 3. Power-down/up sequence example
n System Reset
The AK5353 should be reset once by bringing PDN L after power-up. The internal timing starts clocking by the rising
edge (falling edge at mode1) of LRCK upon exiting from reset.
M0067-E-00
- 13 -
1999/06