AKD4586 Datasheet, PDF (8/46 Pages) Asahi Kasei Microsystems – Evaluation board Rev.B for AK4586

ASAHI KASEI
„ DIP-SW set-up(Setup of interface format and clock mode of AK4103)
[SW1]: No.4-8 set the mode of AK4586 and No.6-10 set the mode of AK4103.
Pin
No.
Name
Contents
1
Reserve
2
Reserve
Always OFF
3
Reserve
4
DIF2
5
DIF1
6
DIF0
AK4103 interface format(see Table 4)
(Default: No.4=ON, No.5,6=OFF: 24bit MSB justified)
7
CKS1
8
CKS0
AK4103 clock mode(see Table 5)
(Default: No.7,8=OFF: 256fs)
Table 3. SW1 set-up
(Note: No.8 is “0” at ON, others are “1” at ON.)
Mode
0
1
2
3
4
5
6
7
Format
No.4 No.5 No.6
DIF2 DIF1 DIF0
16bit, LSB justified
0
0
0
18bit, LSB justified
0
0
1
20bit, LSB justified
0
1
0
24bit, LSB justified
0
1
1
24bit, MSB justified
I²S
1
0
0 Default
1
0
1
24bit, MSB justified (Master) 1
1
0
I²S(Master)
1
1
1
Table 4. AK4103 interface format set-up (1=ON, 0=OFF)
Clock mode
No.7
CKS1
No.8
CKS0
128fs
OFF
ON
256fs
OFF
OFF
384fs
ON
ON
512fs
ON
OFF
Table 5. AK4103 clock mode set-up
Default
[AKD4586]
<KM065102>
8
2005/7