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AK4345_10 Datasheet, PDF (8/27 Pages) Asahi Kasei Microsystems – 100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC with DIT
[AK4345]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.7 ∼ 3.6V; CL = 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Frequency
Half Speed Mode (512/768/1024/1536fs)
fCLK
4.096
36.864
MHz
Normal Speed Mode (256/384/512/768fs)
fCLK
2.048
36.864
MHz
Double Speed Mode (128/192/256/384fs)
fCLK
6.144
36.864
MHz
Duty Cycle
dCLK
40
60
%
LRCK Frequency
Half Speed Mode (DFS1-0 = “10”)
fsh
8
24
kHz
Normal Speed Mode (DFS1-0 = “00”)
fsn
8
48
kHz
Double Speed Mode (DFS1-0 = “01”)
fsd
48
96
kHz
Duty Cycle
dCLK
45
55
%
Audio Interface Timing
BICK Period
Half Speed Mode
tBCK
1/128fs
ns
Normal Speed Mode
tBCK
1/128fs
ns
Double Speed Mode
tBCK
1/64fs
ns
BICK Pulse Width Low
tBCKL
70
ns
Pulse Width High
tBCKH
70
ns
BICK “↑” to LRCK Edge
(Note 11) tBLR
40
ns
LRCK Edge to BICK “↑”
(Note 11) tLRB
40
ns
SDTI Hold Time
tSDH
40
ns
SDTI Setup Time
tSDS
40
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
tCCK
200
tCCKL
80
tCCKH
80
tCDS
40
tCDH
40
tCSW
150
tCSS
150
tCSH
50
tDCD
tCCZ
ns
ns
ns
ns
ns
ns
ns
ns
45
ns
70
ns
Power-Down & Reset Timing
PDN Pulse Width
(Note 12) tPD
4
ms/μF
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK4345 can be reset by bringing PDN pin = “L”.
The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4000× C.
When C = 4.7μF, tPD is 19ms(min).
The value of the capacitor (C) connected with VCOM pin should be 1μF ≤ C ≤ 10μF.
MS0635-E-01
-8-
2010/09