AK4345_10 Datasheet, PDF (12/27 Pages) Asahi Kasei Microsystems – 100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC with DIT

[AK4345]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4345, are MCLK, BICK and LRCK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK
automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 bits (Table 1).
The sampling speed mode is set depending on the MCLK frequency automatically for Auto mode (DFS1 bit = DFS0 bit =
“1”) (Table 2).
The AK4345 is automatically placed in the reset mode when MCLK stops in the normal operation mode (PDN pin = “H”),
and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4345 is powered up. After exiting
reset by PDN pin at power-up etc., the AK4345 is in the reset mode until MCLK and LRCK are input.
Mode
Normal Speed
Double Speed
Half Speed
Auto
DFS1
0
0
1
1
DFS0
fs
0
8 ∼ 48kHz
1
48 ∼ 96kHz
0
8 ∼ 24kHz
1
8 ∼ 96kHz
Table 1. System Clock Example
MCLK Frequency
256/384/512/768fs
128/192/256/384fs
512/768/1024/1536fs
Table 2
MCLK Frequency
512/768fs
128/192/256/384fs
1024/1536fs
Sampling Speed Mode
Normal Speed
Double Speed
Half Speed
Table 2. Auto Mode
Fs
8 ∼ 48kHz
48 ∼ 96kHz
8 ∼ 24kHz
■ Audio Interface Format
The Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 bits as shown in Table 3 can select four
serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of
BICK. Mode 3 can be used for 16bit I²S Compatible format by zeroing the unused LSBs at BICK ≥ 48fs or BICK = 32fs.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
SDTI Format
0
16bit, LSB justified
1
24bit, LSB justified
0
24bit, MSB justified
1
16/24bit, I²S Compatible
Table 3. Audio Interface Format
BICK
≥ 32fs
≥ 48fs
≥ 48fs
≥ 48fs or 32fs
Figure
Figure 10
Figure 11
Figure 12
Figure 13
MS0635-E-01
- 12 -
2010/09