AK4634 Datasheet, PDF (74/77 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

[AK4634]
< MIC differential Input >
DSP
&
µP
0.1µ
10
0.1µ
I2C
DVDD
VSS2
VSS3
NC
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
R1, R2: ≥10Ω
ZD1, ZD2: Required
R1
Speaker
R2 _ZD2
ZD1
SDTO
MCKO
SPN
SVDD
SPP
BICK
SDTI
MCKI
AOUT
Top View
MICN
FCK
CCLK
CDTI
MPI
MICP
PDN
CSN
TST2
VCOM
VCOC
1µ
220
1µ
1k
1k
1µ
0.1µ
Rp Cp
20 k
+ _2.2µ
TST1
VSS1
AVDD
TST3
0.1µ
Analog Supply
2.2∼3.6V
+
10µ
Figure 58. Typical Connection Diagram
Notes:
- VSS1, VSS2 and VSS3 of the AK4634 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open.
- In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 45.
- When the AK4634 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, a pull-up resistor with around 100Ω should be connected to LRCK and BICK pins of the AK4634.
-When AVDD, DVDD and SVDD were distributed, DVDD = 1.6 ~ 3.6 V, SVDD = 2.2 ~ 4.0 V.
Mode
0
1
2
3
6
7
12
13
Others
PLL3
bit
0
0
0
0
0
0
1
1
PLL2 PLL1 PLL0
bit bit bit
PLL Reference
Clock Input Pin
Rp and Cp of
Input Frequency VCOC pin
Rp[Ω] Cp[F]
PLL Lock
Time (max)
0
0
0
FCK pin
1fs
6.8k 220n 160ms
0
0
1
BICK pin
16fs
10k 4.7n
2ms
0
1
0
BICK pin
32fs
10k 4.7n
2ms
0
1
1
BICK pin
64fs
10k 4.7n
2ms
1
1
0
MCKI pin
12MHz
10k 4.7n
30ms
1
1
1
MCKI pin
24MHz
10k 4.7n
30ms
1
0
0
MCKI pin
13.5MHz
10k 10n
30ms
1
0
1
MCKI pin
27MHz
10k 10n
30ms
Others
N/A
Table 45. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
(default)
Rev. 0.5
- 74 -
2007/10