AK5359 Datasheet, PDF (7/18 Pages) Asahi Kasei Microsystems – 24-Bit 192kHz ΔΣ ADC

ASAHI KASEI
[AK5359]
DC CHARACTERISTICS
(Ta=Tmin ∼ Tmax ; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 5.5V)
Parameter
Symbol
min
typ
max
Units
High-Level Input Voltage
VIH
70%VD
-
-
V
Low-Level Input Voltage
VIL
-
-
30%VD
V
High-Level Output Voltage
(Iout=−1mA) VOH
VD−0.5
-
-
V
Low-Level Output Voltage
(Iout=1mA) VOL
-
-
0.5
V
Input Leakage Current
Iin
-
-
±10
µA
SWITCHING CHARACTERISTICS
(Ta=Tmin ∼ Tmax ; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 5.5V; C_L=20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
2.048
0.4/fCLK
0.4/fCLK
LRCK Frequency
Duty Cycle
Slave mode
Master mode
fs
8
45
Audio Interface Timing
Slave mode
SCLK Period
tSCK
72
SCLK Pulse Width Low
tSCKL
33
Pulse Width High
tSCKH
33
LRCK Edge to SCLK “↑”
(Note 10) tLRSH
20
SCLK “↑” to LRCK Edge
(Note 10) tSHLR
20
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
SCLK “↓” to SDTO
tSSD
Master mode
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
fSCK
dSCK
tMSLR
−20
tSSD
−20
Reset Timing
PDN Pulse Width
(Note 11) tPD
150
PDN “↑” to SDTO valid at Slave Mode (Note 12) tPDV
PDN “↑” to SDTO valid at Master Mode (Note 12) tPDV
Note 10. SCLK rising edge must not occur at the same time as LRCK edge.
Note 11. The AK5359 can be reset by bringing the PDN pin = “L”.
Note 12. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
typ
50
64fs
50
4132
4129
max Units
41.472
216
55
MHz
ns
ns
kHz
%
%
ns
ns
ns
ns
ns
25
ns
25
ns
Hz
%
20
ns
20
ns
ns
1/fs
1/fs
MS0428-E-00
-7-
2005/09