AK5359 Datasheet, PDF (10/18 Pages) Asahi Kasei Microsystems – 24-Bit 192kHz ΔΣ ADC

ASAHI KASEI
[AK5359]
OPERATION OVERVIEW
„ System Clock
MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with
MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system
clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF) and master/slave are selected by CKS2-0 pins as
shown in Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5359 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5359 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
96kHz
192kHz
128fs
N/A
N/A
N/A
N/A
24.576MHz
MCLK
192fs
256fs
384fs
N/A
8.192MHz 12.288MHz
N/A
11.2896MHz 16.9344MHz
N/A
12.288MHz 18.432MHz
N/A
24.576MHz 36.864MHz
36.864MHz
N/A
N/A
Table 1. System Clock Example
512fs
16.384MHz
22.5792MHz
24.576MHz
N/A
N/A
768fs
24.576MHz
33.8688MHz
36.864MHz
N/A
N/A
CKS2 CKS1 CKS0 HPF Master/Slave
MCLK
SCLK
128/192fs (108k<fs≤216k)
L
L
L
ON
Slave
256/384fs (8k≤fs≤108k) ≥ 48fs or 32fs
512/768fs (8k≤fs≤54k)
128/192fs (108k<fs≤216k)
L
L
H OFF
Slave
256/384fs (8k≤fs≤108k) ≥ 48fs or 32fs
512/768fs (8k≤fs≤54k)
L
H
L
ON
Master
256fs (8k≤fs≤108k)
64fs
L
H
H
ON
Master
512fs (8k≤fs≤54k)
64fs
H
L
L
ON
Master
128fs (108k<fs≤216k)
64fs
H
L
H
ON
Master
192fs (108k<fs≤216k)
64fs
H
H
L
ON
Master
384fs (8k≤fs≤108k)
64fs
H
H
H
ON
Master
768fs (8k≤fs≤54k)
64fs
Table 2. Mode Select
Note: SDTO outputs 16bit data at SCLK=32fs.
„ Audio Interface Format
Two kinds of data formats can be chosen with the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
0
1
DIF pin
L
H
SDTO
LRCK
SCLK
24bit, MSB justified H/L ≥ 48fs or 32fs
24bit, I²S Compatible L/H ≥ 48fs or 32fs
Table 3. Audio Interface Format
Figure
Figure 1
Figure 2
MS0428-E-00
- 10 -
2005/09