AK4520A Datasheet, PDF (7/19 Pages) Asahi Kasei Microsystems – 100dB 20Bit Stereo ADC & DAC

ASAHI KASEI
[AK4520A]
DIGITAL CHARACTERISTICS
(Ta=25°C; VA,VD=2.7∼5.5V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-100uA)
Low-Level Output Voltage (Iout=100uA)
Input Leakage Current
Symbol
VIH
VIL
VOH
VOL
Iin
min
70%VD
-
VD-0.5
-
-
typ
max
Units
-
-
V
-
30%VD
V
-
-
V
0.5
V
-
±10
uA
SWITCHING CHARACTERISTICS
(Ta=25°C; VA,VD=2.7∼5.5V; CL=20pF)
Parameter
Symbol
min
typ
max
Unit
Master Clock Timing 256fs:
fCLK
4.096
13.824 MHz
Pulse Width Low
tCLKL
27
ns
Pulse Width High
tCLKH
27
ns
384fs:
fCLK
6.144
20.736 MHz
Pulse Width Low
tCLKL
20
ns
Pulse Width High
tCLKH
20
ns
LRCK Frequency
VD=2.7-3.6V
fs
16
44.1
50
kHz
VD=4.5-5.5V
fs
16
44.1
54
Duty Cycle
(Note 11 )
45
55
%
Serial Interface Timing
SCLK Period
tSCK
289.4
ns
SCLK Pulse Width Low
tSCKL
120
ns
Pulse Width High
tSCKH
120
ns
LRCK Edge to SCLK "↑" (Note 12 )
tLRS
30
ns
SCLK "↑" to LRCK Edge (Note 12 )
tSLR
30
ns
LRCK to SDTO(MSB)
SCLK "↓" to SDTO
tLRM
tSSD
100
ns
100
ns
SDTI Hold Time
tSDH
40
ns
SDTI Setup Time
tSDS
40
ns
Reset Timing
PWAD & PWDA Pulse Width
tPW
150
ns
PWAD "↑" to SDTO valid (Note 13 )
tPWV
516
1/fs
Notes: 11.If the duty cycle of LRCK changes larger than 5 to 50%, the AK4520A is reset by the internal phase
circuit automatically.
12.SCLK rising edge must not occur at the same time as LRCK edge.
13.These cycles are the number of LRCK rising from PWAD rising.
0163-E-00
-7-
1997/3