AK4520A Datasheet, PDF (12/19 Pages) Asahi Kasei Microsystems – 100dB 20Bit Stereo ADC & DAC

ASAHI KASEI
[AK4520A]
„ Power-Down & Reset
The ADC and DAC of AK4520A are placed in the power-down mode by bringing each power down pin, PWAD
PWDA "L" independently and each digital filter is also reset at the same time. This reset should always be done
after power-up. In case of the ADC, an analog initialization cycle starts after exiting the power-down mode.
Therefore, the output data, SDTO becomes available after 516 cycles of LRCK clock. This initialization cycle
does not affect the DAC operation.
Figure 5 shows the power-up sequence when the DAC is powered up before the ADC power-up.
{¹ The analog part of ADC is initialized after exiting the power-down state.
{² Digital output corresponding to analog input and analog output corresponding to digital input have
the group delay(GD).
{³ A/D output is "0" data at the power-down state.
{⁴ Click noise occurs at the end of initialization of the analog part. Please mute the digital output
externally if the click noise influences system application. Required muting time depends on the
configuration of the input buffer circuits.
Figure 6: 1s
Figure 9: 200ms
{⁵ Click noise occurs at the edge of PWDA.
{⁶ Please mute the analog output externally if the click noise({⁵ ) influences system application.
Figure 5 . Power-up sequence
0163-E-00
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1997/3