AK2500B Datasheet, PDF (7/17 Pages) Asahi Kasei Microsystems – DS3/STS-1 Analog Line Receiver

ASAHI KASEI
[AK2500B]
Output Jitter
Typical output jitter characteristics is shown in the table of ANALOG SPECIFICATIONS (page.11).
Jitter Transfer
Jitter transfer characteristics is shown in the table of ANALOG SPECIFICATIONS (page.11).
Jitter Tolerance
Compliance with GR-499-CORE, GR-253-CORE, ITU-T G.752, G.824
Typical jitter tolerance characteristics is shown in the table of ANALOG SPECIFICATIONS (page.11).
Loss-of-Lock Detection
If the recovered clock frequency is larger than approximately 0.5% of EXCLK, RLOL alarm goes High.
External Reference Clock
An external reference clock EXCLK is used to set the frequency of the PLL. The frequency of EXCLK should be
within the ideal clock±100ppm.
Reset
AK2500B/01B goes into RESET status if _RESET input is low.
Output pins status is as follows during the low input on _RESET .
RLOS, RLOL
: High
RPDATA, RNDATA, RCLK : Low
MS0005-E-00
-7-
1999/12