AK2500B Datasheet, PDF (12/17 Pages) Asahi Kasei Microsystems – DS3/STS-1 Analog Line Receiver

ASAHI KASEI
[AK2500B]
DS3 SWITCHING SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V+ )
Parameter
Symbol Min Typ Max
RCLK Pulse Width
(Note 10, 11)
EXCLK Duty Cycle (EXCLK Min Rise/Fall time : 5ns)
Rise Time, RCLK
(Note 11)
Fall Time, RCLK
(Note 11)
Delay time from RCLK rising to RDATA(Note 12)
Setup time from RCLK falling to RDATA(Note 12)
Hold time from RCLK falling to RDATA(Note 12)
tpwh
tpwl
tpwh1
tr
tf
tdcrd
tscrd
thcrd
10.1 11.177 12.2
10.1 11.177 12.2
40
-
60
-
-
3.5
-
-
3.5
0
-
3.5
5.0
-
-
8.4
-
-
Units
ns
ns
%
ns
ns
ns
ns
ns
STS-1 SWITCHING SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V+ )
Parameter
Symbol Min Typ Max
Units
RCLK Pulse Width
(Note 11, 13)
tpwh
8.7 9.645 10.6
ns
tpwl
8.7 9.645 10.6
ns
EXCLK Duty Cycle(EXCLK Min Rise/Fall time : 5ns) tpwh1/tpw 40
-
60
%
Rise Time, RCLK
(Note 11)
tr
-
-
3.5
ns
Fall Time, RCLK
(Note 11)
tf
-
-
3.5
ns
Delay time from RCLK rising to RDATA(Note 12) tdcrd
0
-
3.5
ns
Setup time from RCLK falling to RDATA(Note 12) tscrd
5.0
-
-
ns
Hold time from RCLK falling to RDATA(Note 12) thcrd
7.0
-
-
ns
Note; 10.
11.
12.
13.
Assumes PLL is locked to 44.736 MHz signal.
The sum of the pulse widths must always meet the frequency specifications.
At max load of 10 pF.
Assumes PLL is locked to 51.84 MHz signal.
DIGITAL CHARACTERISTICS
(TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V)
Parameter
Symbol
Min
Typ
High-Level Input Voltage (Note 14)
VIH (V+) x 0.7 -
Low-Level Input Voltage (Note 14)
High-Level Output Voltage(Note 15,16)
IOUT=-40uA
Low-Level Output Voltage
IOUT=1.6mA (Note 15), 0.4mA (Note 16)
Input Leakage Current (Note 17)
Note; 14. Pins RESET
15. Pins RCLK, RPDATA, RNDATA
VIL
GND
-
VOH (V+) x 0.8 -
VOL
GND
-
16. Pins RLOS, RLOL
17. Except RESET
Max Units
(V+)
V
0.5
V
(V+)
V
0.4
V
±10
uA
MS0005-E-00
- 12 -
1999/12