AKD5701 Datasheet, PDF (6/40 Pages) Asahi Kasei Microsystems – AK5701 Evaluation board Rev.0

ASAHI KASEI
[AKD5701-A]
(3) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: BCLK or LRCK pin)
Connect PORT4 (DSP2) with DSP.


Figure below shows PORT4 pin assign.



PORT4
MCKI
EXBCLK
EXLRCK
EXSDTI
VD
GND
GND
NC
NC
SDTO
a) Set up jumper pins of MCKI clock
JP16
XTI
JP19
MCLK_SEL
5701-
MCKO
EXTCLK
/BCLK
4114- MCKI EXTCLK
MCKO
/BCLK
b) Set up jumper pins of BCLK clock
When an external clock is supplied through a RCA connector J3 (EXT/BCLK), J4 (EXT/LRCK), JP14 (EXT1)
and R20, JP15 (EXT2) and R21 should be properly selected in order to much the output impedance of the clock
generator.
JP17
BCLK_SEL
JP12
BCLK
EXT EXT EXTBCLK/ BCLK/
BCLK
DIT
DIT
c) Set up jumper pins of LRCK clock
JP18
LRCK_SEL
64fs 32fs 16fs
JP13
LRCK
EXT EXT EXTLRCK/ LRCK/
LRCK DIT
DIT
2fs 1fs
<KM076903>
-6-
2005/04