AKD4118A-A Datasheet, PDF (6/23 Pages) Asahi Kasei Microsystems – AK4118A Evaluation Board Rev.0

[AKD4118A-A]
b-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of
MCKO1/MCKO2 sets up by OCKS 1-0.
Output
signal
JP12
MCKO1 MCKO1 Default
MCKO2 MCKO2
Table 12. Selection of MCKO1/MCKO2
OCKS1 pin
(SW3_2)
OCKS1 bit
0
0
1
1
OCKS0 pin
(SW3_3)
OCKS0 bit
(X’tal)
MCKO1 MCKO2
0
256fs
256fs
256fs
1
256fs
256fs
128fs
0
512fs
512fs
256fs
1
128fs
128fs
64fs
Table 13. Master Clock Frequency Select
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
Default
b-2. Set-up of input/output of BICK and LRCK
Please set up SW 3_8 (DIT_I/O) according to the setup of audio format of AK4118A (Refer to Table 20).
JP16 and 17 should be fixed to the “DC” side.
Audio format
SW3_8 (DIT_I/O)
Slave mode
0
Master mode
1
Table 14. Set-up of DIT_I/O
Default
c. Set-up of audio data format
Please refer to Table 7.
d. Set-up of CM1 and CM0
CM1 pin CM0 pin
SDTO
(SW3_1) (JP18) (UNLOCK) PLL
X'tal
Clock source
source
CM1 bit CM0 bit
0
0
-
ON ON(Note) PLL(RX)
RX Default
0
1
-
OFF
ON
X'tal
DAUX
1
0
0
ON
ON
PLL(RX)
RX
1
ON
ON
X'tal
DAUX
1
1
-
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 15. Clock Operation Mode Select
[KM100300]
-6-
2009/08