AKD4118A-A Datasheet, PDF (5/23 Pages) Asahi Kasei Microsystems – AK4118A Evaluation Board Rev.0

[AKD4118A-A]
(2) Evaluation for DIT
Serial Data in(10pin port) – AK4118A – S/PDIF out(optical or BNC)
ADC
MCLK
BIC K
LRCK
DAUX *
PORT2
(10pin Header)
* Input to the fifth pin.
MC LK
B ICK
LRCK
DAUX
AK4118A
(DIT)
Optical, XLR or
BNC connector
AKD4118A-A
S/PDIF
MCLK, BICK, LRCK and DAUX are input the via 10pin header (PORT2: DIR).
a.Set-up of a Bi-phase output signal
TX0 and TX1 should not select an optical connector or a BNC connector at the same time.
a-1. The data outputted from TX1 can be selected by OPS12-10 bit.
Connector
JP19 (TX1)
Optical (PORT4)
OPT
BNC (J4)
BNC
Table 9. Set-up of TX1
JP14 (TX1)
BNC
BNC
a-2. As for TX0, only the loop back mode of RX corresponds. This mode is fixed to RX0 in parallel mode. In
serial mode, it can be selected by OPS02-00 bits.
Connector
Optical (PORT4)
BNC (J4)
JP13 (TX0) JP19 (TXP1)
OPT
Open
BNC
Open
Table 10. Set-up of TX0
JP14 (TXN1)
BNC
BNC
b.Set-up of clock input and output
The used signals are MCLK, LRCK, BICK, and DAUX.
The signal level outputted and inputted from PORT2 is 3.3V.
PORT2
DIR
1
5
10
6
Figure 3. PORT2 pin layout
Clock
MCLK
BICK
LRCK
DAUX
PORT
PORT2
PORT2
PORT2
PORT2
Table 11. Clock input/output
I/O
OUT
IN / OUT
IN / OUT
IN
[KM100300]
-5-
2009/08