AK8131S Datasheet, PDF (6/8 Pages) Asahi Kasei Microsystems – Low Power Multiclock Generator with VCXO

AK8131S
The brand name
of AKEMD’s IC’s
Typical Connection Diagram
+3.3V typ.
MPEG-TS
DECODER
CTL OUT2
CTL OUT0
CTL OUT1
DC Voltage
CTL OUT
(PWM)
R11
C11
C1
REF CLK IN
GND
27.0MHz AT Cut Crystal
Cext1
Cext2
AK8131S
1:X1
2:S0
3:S1
4:VIN
5:VDD1
6:GND1
7:CLK1
8:CLK2
X2:16
VDD3:15
S2:14
VDD2:13
GND2:12
CLK4:11
CLK3:10
REFOUT:9
C3
C2
ENC etc
27.000MHz
ENC etc
27.000MHz
LVDS I/F
66.0,74.25,
82.0MHz
HDMI LVDS I/F
74.25,74.1758MHz
Figure 2: Typical Connection Diagram
C1, C2, C3: 0.1µF
Cext1, Cext2: Depends on crystal characteristics. Refer the specification of the crystal.
R11, C11: In case of interface by PWM. For right configuration, refer the specification of the
applied processor.
PCB Layout Consideration
The AK8131S is a high-accuracy and low-jitter multi clock generator. For proper performances specified
in this datasheet, careful PCB layout should be taken. The followings are layout guidelines based on the
typical connection diagram shown in Figure 2
Power supply line – AK8131S has three power supply pins (VDD1-3) which deliver power to internal
circuitry segments. A 0.1µF decoupling capacitor should be placed as close to each VDD pin as possible.
Ground pin connection – AK8131S has two ground pins (GND1-2). These pin require connecting to
plane ground which will eliminate any common impedance with other critical switching signal return.
0.1µF decoupling capacitors placed at VDD1, VDD2, and VDD3 should be grounded at close to the
GND1pin, the GND2 pin, and the GND2, respectively.
Crystal connection – Proper oscillation performance and pullable range are susceptible to stray or
parasitic capacitors around crystal. The wiring traces to a crystal form X1 (Pin 1) and X2 (Pin 14) have
equal lengths with no via and as short in length as possible. These traces should be also located away
from any traces with switching signal.
Feb-08
MS0688-E-01
-6-