AK7722 Datasheet, PDF (6/28 Pages) Asahi Kasei Microsystems – 24bit 4ch ADC + 24bit 4ch DAC with Audio DSP

[AK7722]
PIN FUNCTION
No. Name
1 AINL3
2 AINR2N
3 AINR2P
4 AINL2N
5 AINL2P
6 AINR1N
7 AINR1P
8 AINL1N
9 AINL1P
10 AVDD
11 VSS1
12 LFLT
13 TESTI1
14 GLRCKI
15 GBICKI
16 SDIN5
17 DVDD
18 VSS2
19 XTI
20 XTO
21 GP1
22 JX0
23 LRCKI
24 BICKI
25 SDIN1
SDIN2
26
JX1
27 SRLRCK1
28 SRBICK1
I/O
Function
Classification
I ADC1 Lch Single-ended Input 3 Pin.
Analog Input
I ADC1 Inverted Rch Differential Input 2 Pin
Analog Input
I ADC1 Non-inverted Rch Differential Input 2 Pin
Analog Input
I ADC1 Inverted Lch Differential Input 2 Pin
Analog Input
I ADC1 Non-inverted Lch Differential Input 2 Pin
Analog Input
I ADC1 Inverted Rch Differential Input 1 Pin
Analog Input
I ADC1 Non-inverted Rch Differential Input 1 Pin
Analog Input
I ADC1 Inverted Lch Differential Input 1 Pin
Analog Input
I ADC1 Non-inverted Lch Differential Input 1 Pin
Analog Input
- Analog Power Supply Pin 3.0 ~ 3.6V
Power Supply
- Analog Ground Pin 0V
Power Supply
O R and C Component Connect Pin for PLL
Refer to “7. LFLT Pin External Connection”. This pin outputs “L” during Analog Output
initial reset.
I Test 1 Pin (Internal pull-down)
This pin must be connected to VSS.
Test
I Frame Clock Input Pin for Voice Guidance
Digital Input
I Bit Clock Input Pin for Voice Guidance
Digital Input
I Serial Audio Input Pin for Voice Guidance
Digital Input
- Digital Power Supply Pin 3.0~3.6V
Power Supply
- Ground Pin 0V
Power Supply
Crystal oscillator input pin
I Connect a crystal oscillator between this pin and the XTO pin, or input an
Clock
external clock to the XTI pin.
Crystal Oscillator Output Pin
O
When a crystal oscillator is used, connect it between XTI and XTO. When
an external clock is used, leave this pin open. During initial reset, the output
Clock
of this pin is not determinable.
O
Programmable Bit Output Pin
This pin outputs “L” during initial reset.
Digital Output
Conditional Jump Pin0
I ^{The conditional jump pin (JX0) is valid by setting control register (JX0E) to} Conditional Input
“1”.
I
LR Channel Select Clock Pin 1
LR clock should be input to this pin in slave mode.
Serial Bit Clock Input Pin 1
I _{BITCLOCK (48fs or 64fs) should be input to this pin in slave mode.}
System Clock
Input
System Clock
Input
I Serial Data Input 1 Pin
Digital Input
I Serial Data Input 2 Pin
Digital Input
Conditional Jump Pin1
I The conditional jump pin (JX1) is valid by setting control register (JX1E) to Conditional Input
“1”.
I LR Channel Select Clock Pin 1 (for SRC)
System Clock
Input
I Serial Bit Clock Input Pin 1 (for SRC)
System Clock
Input
MS1328-E-00-PB
6
2011/09