AK7722 Datasheet, PDF (18/28 Pages) Asahi Kasei Microsystems – 24bit 4ch ADC + 24bit 4ch DAC with Audio DSP

[AK7722]
■ Audio Interface (SDIN1-2, SRIN1-3, SDOUT1-3)
(Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V, CL=20pF)
Parameter
DSP Section Input SDIN1-2, SRIN1-3
(Note 31)
Delay Time from BICKI “↑” to LRCKI
(Note 32)
Symbol min
tBLRD
20
typ max Unit
ns
Delay Time from LRCKI to BICKI “↑”
(Note 32)
tLRBD
20
ns
Serial Data Input Latch Setup Time
tBSIDS
80
ns
Serial Data Input Latch Hold Time
tBSIDH
80
ns
SRC Section Input SRIN1-3
(Note 33)
Delay Time from SRBICK1-3 “↑” to SRLRCK1-3 (Note 34) tBLRD
20
ns
Delay Time from SRLRCK1-3 to SRBICK1-3 “↑” (Note 34) tLRBD
20
ns
Serial Data Input Latch Setup Time
tBSIDS
40
ns
Serial Data Input Latch Hold Time
tBSIDH
40
ns
Output SDOUT1-3
(Note 31)
BICKO Frequency
fBCLK
64
fs
BICKO Duty Factor
50
%
Delay Time from BICKO “↓” to LRCKO
(Note 35) tBLRD
-20
40
ns
Delay Time from LRCKI to Serial Data Output
(Note 36) tLRD
80
ns
Delay Time from BICKI to Serial Data Output
(Note 33) tBSOD
80
ns
Delay Time from LRCKO to Serial Data Output
(Note 36) tLRD
80
ns
Delay Time from BICKO to Serial Data Output
(Note 33) tBSOD
80
ns
SDINn → SDOUTn (n=1-2)
(Note 37)
Delay Time from SDINn to SDOUTn Data Output
tIOD
60 ns
Note 31. BICKI=SRBICKn (n=1, 2, 3) in CKM mode 4.
Note 32. BICKI edge must not occur at the same time as LRCKI edge. The BICKI polarity is inverted in PCM mode
0/2.
Note 33. Except CKM mode 4
Note 34. SRBICK1-3 edge must not occur at the same time as SRLRCK1-3 edge. When BIEDGE bit= “1”, this value is
for SRBICK1-3 “↓” since SRBICK1-3 are polarity reversal.
Note 35. When SELBCK bit= “1”, this value is for BICKO “↑” since BICKO is polarity reversal.
Note 36. Except I²S.
Note 37. SDIN1 → SDOUT1: Control Register Setting, SELDO1[1:0]=1h, OUT1E bit= “1”
SDIN2/JX1 → SDOUT2: Control Register Setting, SELDO2[1:0]=1h, OUT2E bit= “1”
SRIN1/SDIN3 → SDOUT3: Control Register Setting, SELDI3 bit = “1”, SELDO3[1:0]=1h, OUT3E bit= “1”
MS1328-E-00-PB
18
2011/09