AK5558VN_16 Datasheet, PDF (57/70 Pages) Asahi Kasei Microsystems – 8-Channel Differential 32-bit ADC

[2] DSD mode
The Internal PDN is released by inputting MCLK after setting the PDN pin to “H”.
[AK5558]
PDN pin
Internal PDN
(1)
MCLK In
Don’t care
Internal
State
ADC In
(Analog)
Power-Down
Initialize
(2)
Normal Operation
(6)
(4)
Don’t care
Power-Down
OVF-pin
DSD Out
(Digital)
(3)
“L” (-full scale data)
normal data
(5)
abnormal data
normal data
“L” (-full scale data)
Figure 61. DSD Operation Timing
Notes:
(1) The internal LDO is powered up by releasing PDN pin to “H”. The internal PDN is released by
toggling internal oscillator clock for 16384 times (max. 10ms).
The internal PDN is released in max. 1 ms after releasing PDN pin to “H”.
Register writings become available when the internal PDN changes to “1”.
During this period, digital output and digital in/output pins may output an instantaneous pulse (max.
1 us). Therefore, referring the output of digital pins and data transmission with a device on the same
3-wire serial/I²C bus as the AK5558 should be avoided in this period to prevent system errors.
(2) Initialization operation will be completed in 583/fs.
(3) DSD output pins output “L” (-full scale data) during power down and initializing operation. DSD
output pins output full scale data during phase modulation mode, a reset sequence and a CH power
down status.
(4) The OVF pin outputs “H” when an excessive signal is input and overflow is detected at internal
modulator. The OVF pin status will change after group delay period from the excessive input.
(5) In the case above (4), the DSD output data will not be correct.
(6) The OVF pin returns to “L” when the input signal settled to a normal state and overflow status of the
internal modulator is resolved. The OVF pin status will change after group delay period from the
normal input.
015099850-E-00
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2016/03