AKD4394_07 Datasheet, PDF (5/32 Pages) Asahi Kasei Microsystems – 192kHz sampling 24Bit ΔΣ DAC.

ASAHI KASEI


[AKD4394]
(3) Using AD converted data
AD converted data from AKM’s AD evaluation boards(AKD539X, AKD535X) is used through PORT1.
* In case of using external clock through a BNC connector, select EXT of JP9 and short JP1.
* In case of using the double speed sampling mode, select 1/2X of JP8 and set S2-2(DFS) on.
JP1 ^JP2
JP4
JP5
VDD
GND
XTL
CS8414
INV
THR
BCP
XTL/EXT
DIR
BI
JP6
JP7
DIR
XTL/EXT
SD
LR
JP8
2X
1X
JP14
1/2X
1X
JP9
DIR
XTL
CKDIV1 CKDIV2
EXT
CLK
Fig.5 Jumper set-up (A/D)
(4) All interface signals including master clock are fed externally.
Under the following set-up, MCLK, LRCK and SCLK signals needed for the D/A to operate could be fed through PORT1.
JP1 ^JP2
JP4
JP5
XTL
VDD
GND
CS8414
INV
THR
BCP
XTL/EXT
DIR
BI
JP6
JP7
DIR
XTL/EXT
SD
LR
Fig.6 Jumper set-up (ext.)
JP8
JP14
JP9
2X
1/2X ^DIR
1X
1X XTL
CKDIV1 CKDIV2
EXT
CLK
2. MCLK set-up
When the LRCK is fed from the 74HC4040 on the board, The ratio of MCLK to LRCK can be selected by JP8 and JP14.
JP14
1X
1X
1/2X
1/2X
JP8
X'tal
MCLK
fs
1X
12.288MHz 12.288MHz 48kHz
2X
24.576MHz 24.576MHz 48kHz
1X
24.576MHz 12.288MHz 96kHz
2X
49.152MHz 12.288MHz 96kHz
MCLK/LRCK
256
512
128
128
Table.1 set-up example
3. BICK set-up
When BICK is supplied from U1(74HC4040), either 32fs or 64fs could be
selected. Fig.8 shows 64fs mode. 64fs mode is recommended.
*Only mode 0(LSB justified 16bit mode) can correspond to 32fs.
JP3
64
32
BCS
Fig.7 Jumper Set-up (BCS)
<KM063002>
5
’07/01