AK93C45A Datasheet, PDF (5/14 Pages) Asahi Kasei Microsystems – 1K / 2K / 4K / 8KBIT SERIAL CMOS EEPROM

ASAHI KASEI
[AK93C45A/55A/65A/75A]
WRITE
The write instruction is followed by 16 bits of data to be written into the specified address. After the
last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the
SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates
the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs).
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
CS
SK
012345
8 9 10 11
23 24 25 ^tCS
DI
0 1 0 1 A5 A4
A1 A0 D15 D14
D2 D1 D0
DO
Start Bit
Op code
Hi-Z
AK93C45A output a logic "1" (Ready status),
if previous instruction is WRITE.
Busy
Ready
tE/W
WRITE (AK93C45A)
CS
SK
012345
10 11 12 13
DI
DO
01
Start Bit
0
1 X / A7 A6
Op code
Hi-Z
A1 A0 D15 D14
AK93C55A/65A output a logic "1" (Ready status),
if previous instruction is WRITE.
*Address bit A7 becomes a "don't care" for AK93C55A.
WRITE (AK93C55A/65A)
25 26 27 ^tCS
D2 D1 D0
Busy
Ready
tE/W
X: Don't care
CS
SK
012345
12 13 14 15
27 28 29 ^tCS
DI
0 1 0 1 X A8
A1 A0 D15 D14
D2 D1 D0
Start Bit Op code
DO
Hi-Z
AK93C75A output a logic "1" (Ready status),
if previous instruction is WRITE.
WRITE (AK93C75A)
Busy
Ready
tE/W
X: Don't care
DAM01E-02
-5-
2002/06