AK8122E Datasheet, PDF (5/9 Pages) Asahi Kasei Microsystems – Differential Zero Delay Clock Buffer

The brand name
of AKEMD’s IC’s
Standards of Jitter
AK8122
Fig.1 Delay (Static Phase Offset + Skew) : Tdly = ΣTdly/N
Fig.2 Period jitter: Tpj = Tcycn – 1/f0
Fig.3 Cycle to cycle jitter: Tc2cj=Tcn-Tcn+1
Fig.4 Half period jitter: Thpj = Thp – 1/2*f0
MS0971-E-00
Fig.5 Input and Output Slew Rate
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Dec-10