AK6440BL Datasheet, PDF (5/13 Pages) Asahi Kasei Microsystems – 4096bit Serial CMOS EEPROM

ASAHI KASEI
[AK6440B]
Functional Description
The AK6440B has 4 instructions such as READ, WRITE, WREN (write enable) and WRDS
(write disable). Each instruction is organized by op-code block (8bits), address block (8bits)
and data (8bits×2). When input level of SK pin is high level and input level of chip select
(CS) pin is changed from high level to low level, AK6440B can receive the instructions.
When the instructions are executed consecutively, the CS pin should be brought to high
level for a minimum of 250ns(tCS) between consecutive instruction cycle.
 Instruction Set
Instruction
Op-Code
Address
Data
WRITE
10100100 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0(IN)
READ
10101000 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0(OUT)
WREN
10100011
XX X X X X X X
WRDS
10100000
XX X X X X X X
(WRAL)
10101111
X X X X X X X X D15-D0(IN)
X: don’t care
(Note) The WRAL instruction is used for factory function test only. User can't use this
instruction.
Write
The write instruction is followed by 16 bits of data to be written into the specified address.
After the 32nd rising edge of SK to read D0 in, the AK6440B will be put into the automatic
write time-out period. During the automatic write time-out period (Busy status) and while
entering write instruction, the RESET pin should be low level. If the RESET pin is set to
high level during the automatic write time-out period, the AK6440B stops execution of
internal programming and the device returns to ready status. In this case the word data of
the specified address will be incomplete. When inputting the new instruction after RESET,
the CS pin should be set to high level. When the RESET pin is kept at high level, the write is
not executed. This becomes write protection function.
The CS pin need not be high level during automatic write time-out period (BUSY status).
RESET
CS
SK
DI
DO
1 2 3 4 5 6 7 8 9 10
1 0 1 0 0 1 0 0 A7 A6
Hi-Z
15 16 17 18
A1 A0 D15 D14
30 31 32
D2 D1 D0
tE/W
WRITE
DAS03E-01
-5-
2012/09