AK6440BL Datasheet, PDF (4/13 Pages) Asahi Kasei Microsystems – 4096bit Serial CMOS EEPROM

ASAHI KASEI
[AK6440B]
Pin Description
CS (Chip Select)
When SK is high level and CS is changed from high level to low level, AK6440B can receive
the instructions. CS should be kept low level while receiving op-code, address and data
and while outputting data.
If CS is changed to high level during the above period, AK6440B stops the instruction
execution.
When SK is low and CS is changed from high level to low level, AK6440B will be in status
output mode. The CS need not be low level during the automatic write time-out period
(BUSY status).
SK (Serial Clock)
The SK clock pin is the synchronous clock input for input/output data. At write operation,
AK6440B takes in the write data from data input pin (DI) synchronously with rising edge of
input pulse of serial clock pin (SK). And at read operation, AK6440B takes out the read
data to data output pin (DO) synchronously with falling edge of SK. The SK clock is not
needed during the automatic write time-out period (BUSY status), the status output period
and when the device isn't selected (CS = high level).
DI (Data Input)
The op-code, address and write data is input to the DI pin.
DO (Data Output)
The DO pin outputs the read data and status signal and will be high impedance except for
this timing.
RESET (Reset)
The AK6440B stops executing the write instruction when the RESET pin is high level. The
RESET pin should be low level while the write instruction input period and the automatic
write time-out period. If the RESET pin is high level while the automatic write time-out
period, the AK6440B stops execution of internal programming and the device returns to
ready status. In this case the word data of the specified address will be incomplete.
When inputting the new instruction after RESET, the CS pin should be set to high level.
The read, write enable and write disable instructions are not affected by RESET pin status.
VCC (Power Supply)
GND (Ground)
DAS03E-01
-4-
2012/09