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AK4436 Datasheet, PDF (46/63 Pages) Asahi Kasei Microsystems – 108dB 768kHz 32bit 6-Channel Audio DAC | |||
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[AK4436]
(2) Clock Synchronization Sequence with RSTN-bit
The DZF pin outputs âHâ by setting RSTN bit to â0â. The DAC is reset after 3~4/fs from the DZF pin = âHâ,
and the analog output goes to VCOM voltage. The synchronization function is enabled when the DZF pin
= âHâ. Figure 36 shows synchronization sequence with RSTN bit.
RSTN bit
Internal
RSTN bit
3~4/fs (4)
2~3/fs (4)
Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
D/A In
(Digital)
D/A Out
(Analog)
forceâ0â (2)
(3)
GD
(5)
(5)
DZF
2/fs(4)
Internal Counter
Reset
Operation (1)
GD (3)
Internal
Data Reset
4~5/fs (2)
Notes:
(1) The DZF pin outputs âHâ by a falling edge of RSTN bit, and returns to âLâ after 2/fs from the internal
rising edge of RSTN bit. During this period the synchronization function is enabled.
(2) Internal data is fixed to â0â for 4~5/fs forcibly when the internal counter is reset.
(3) The analog output corresponding to digital input has group delay (GD). It is recommended that
when writing â0â data to RSTN bit, â0â period should be longer than the GD period.
(4) It takes 3~4/fs to fall down and 2~3/fs to rise up for the internal RSTN signal from RSTN bit writing.
There is a case that the internal counter is reset before internal RSTN bit is changed to â1â since the
synchronization function becomes enabled immediately by setting RSTN bit = â0â.
(5) A click noise occurs by an internal RSTN signal edge or an internal counter reset. This noise is
output even if â0â data is input. Mute the analog output externally if the click noise adversely affects
the system performance.
Figure 36. Clock Synchronization Sequence by RSTN bit
016001934-E-00
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2016/03
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