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AK4436 Datasheet, PDF (45/63 Pages) Asahi Kasei Microsystems – 108dB 768kHz 32bit 6-Channel Audio DAC | |||
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[AK4436]
â Clock Synchronization
The AK4436 has a function that resets the internal counter to keep a falling edge of the internal FSI clock
is in 3/256fs from an edge of the external FSI clock. Clock synchronization function becomes valid when
data at all channels are continuously â0â for 8192 times if SYNCE bit is set to â1â during operation in PCM
mode or when RSTN bit is set to â0â. The operation clock is synchronized to a falling edge of LRCK in
PCM mode and a rising edge of LRCK in I2C mode.
The analog output becomes VCOM voltage when RSTN bit = â0â or zero data is detected. Figure 35
shows a synchronization sequence when the input data is â0â for 8192 times continuously. Figure 36
shows a synchronization sequence by RSTN bit.
(1) Clock Synchronization Sequence when Input Data is â0â for 8192 Cycles Continuously
The DZF pin goes to âHâ and the synchronization function becomes enabled when input data is â0â for
8192 time continuously including when the data is attenuated. Figure 35 shows a synchronization
sequence.
D/A In
(Digital)
SMUTE
ATT_Level
Attenuation
GD
AOUT
(1)
(1)
-ï¥
GD
GD
(4)
DZF pin
Internal Counter
Reset
Internal
Data Reset
(2)
8192/fs
Operation (2)
4~5/fs (3)
(2)
8192/fs
Operation (2)
(5)
Notes:
(1) Refer to Table 14 internal transition time of ATT.
(2) The synchronization function becomes enabled when all channels input data are â0â for 8192 times
continuously.
(3) Internal data is fixed to â0â for 4~5/fs forcibly when the internal counter is reset.
(4) Click noise occurs when the internal counter is reset. This noise is output even if â0â data is input.
Mute the analog output externally if this click noise adversely affects system performance.
(5) The internal counter will not be reset when the internal and the external clocks are synchronized
even if the synchronization function is enabled.
Figure 35. Clock Synchronization Sequence with Continuous Zero Data
016001934-E-00
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2016/03
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