AKD4371-B Datasheet, PDF (4/33 Pages) Asahi Kasei Microsystems – 24bit DAC with Headphone Amplifier

(2) PLL Slave Mode
(2-1) PLL Reference Clock : MCKI pin
[AKD4371-B]
AK4371
MCKI
MCKO
BICK
LRCK
SDATA
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
DSP or μP
256fs/128fs/64fs/32fs
32fs ~ 64fs
1fs
MCLK
BCLK
LRCK
SDTO
Figure 3. PLL Master Mode (PLL Reference Clock : MCKI pin)
PORT2 (DSP) is used. Nothing should be connected to PORT1(DIR).
MCKO is needed for a synchronous signal of BICK and LRCK.
MCLK,BICK,LRCK and SDATA are supplied from PORT2. The test pin(MCKO) should be connected to
MCLK of DSP.
Set up the jumper pins.
JP3
LRCK2
JP4
BICK2
JP5
MCLK
JP6
BICK
JP7
LRCK
JP8
SDTO
<KM086201>
-4-
2007/07